A Low Power Low Inrush Current LDO with Different Techniques for PSR and Stability Improvement

One of the most popular power management regulators is low drop-out voltage regulator (LDO). LDOs have different specifications such as supply rejection (PSR) over frequencies, stability load ranges, inrush current spike flows through input supply, and consumption. In this work, we present a LDO design with techniques for PSR improvement across frequencies. The presented in work low-power small area but achieves high wide range designed 65 nm CMOS technology better than 80 dB up to 30 MHz an output 25 mA using capacitor 4 µF. can be used capless/capped ranges 200 from 1 nF 12 µF by more 2×. consumes zero-load quiescent 10 µA its 180 µm × µm.