Retina-Motivated CMOS Vision Chip Based on Column Parallel Architecture and Switch-Selective Resistive Network
نویسندگان
چکیده
منابع مشابه
Column-Parallel Vision Chip Architecture for High-Resolution Line-of-Sight Detection Including Saccade
Although the line-of-sight (LoS) is expected to be useful as input methodology for computer systems, the application area of the conventional LoS detection system composed of video camera and image processor is restricted in the specialized area, such as academic research, due to its large size and high cost. There is a rapid eye motion, so called ‘saccade’ in our eye motion, which is expected ...
متن کاملOn-chip parallel and network-based systems
General Scope In order to achieve functionality with low energy speed product, on-chip parallel and networkbased system design requires larger device, multi block functions, and energy evaluation schemes. Such systems, which are emerging as the architecture of choice for future high performance processors, require efficient interconnect which are necessary to satisfy the data supply needs of al...
متن کاملParallel WAN Switch Based on Neural Network
The article deals with a WAN switch design based on a Feedforward neural network, specifically for the Feedforward Backpropagation algorithm. The designed switch is fully parallel, uses neural network for switch management and also for traffic engineering. The switch uses advanced packet dropping mechanism. The article describes the switch design (network processor design) and compares the deve...
متن کاملA CMOS feedforward neural-network chip with on-chip parallel learning for oscillation cancellation
The paper presents a mixed signal CMOS feedforward neural-network chip with on-chip error-reduction hardware for real-time adaptation. The chip has compact on-chip weighs capable of high-speed parallel learning; the implemented learning algorithm is a genetic random search algorithm: the random weight change (RWC) algorithm. The algorithm does not require a known desired neural network output f...
متن کاملOptimized architecture and design of an output-queued CMOS switch chip
Traditional improvements in packet switch architecture aimed at increasing switch performance in terms of utilization, fairness and QoS. This paper focuses on improving architecture to achieve implementation feasibility of terabit aggregate data rates while maintaining such performance. Terabit class shared-memory switch chips are simple in concept but are a challenge to build due to the memory...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: ETRI Journal
سال: 2008
ISSN: 1225-6463
DOI: 10.4218/etrij.08.0108.0263