BOA: The Architecture of a Binary Translation Processor

High frequency design and instruction-level parallelism (ILP) are two keys to high performance microprocessor implementation. To achieve these sometimes competing goals, the Binary-translation Optimized Architecture (BOA) aims to bring code translation techniques based on continuous profiling into the mainstream. Initially, code is interpreted to detect code hot spots and gather profile information to guide dynamic optimizations. To achieve compatibility with the established PowerPC architecture, a binary translation layer translates PowerPC instructions into simple VLIW operation primitives. These primitives are then scheduled using VLIW scheduling techniques to a variable length, six issue VLIW/EPIC processor. Binary translation eliminates the binary compatibility problem faced by other processors, while dynamic recompilation enables adaptive re-optimization of critical program code sections and eliminates the need for dynamic scheduling hardware. As a result, the BOA execution platform can be designed for multiple Gigahertz operation. The hardware execution platform includes novel microarchitectural features to eliminate complex stall and exception logic. Special support is also provided for binary translation in the form of several primitives designed for system-level binary translation functions. The data types of the binary translation processor are similar to that of the emulated PowerPC architecture to eliminate data representation issues which could necessitate potentially expensive data format conversion operations. In this work we examine the implications of binary translation on processor architecture and software translation and how we support a very high frequency PowerPC implementation via dynamic binary translation.