Virtual Inputs Virtual Outputs
نویسنده
چکیده
We have developed a formal validation tool that has been used in several projects that are developing software for AT&T's 5ESS TM telephone switching system. The tool validates networks of communicating processes speciied in the Virtual Finite State Machine (VFSM) notation, which is used during the low-level-design phase of software development to specify the control behavior of an implementation. The VFSM validator performs a reachability analysis, using Holz-mann's bitstate-hashing technique Ho88], to check for errors in VFSM communication such as deadlock, live-lock and unexpected inputs. In this paper, we present an overview of the VFSM methodology and validator, report on the present status of the VFSM validation eeort, and discuss some of the lessons we have learned about the proper role of formal validation in the software development process.
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