Rapid Semiconductor Process Design within the Vista Framework: Integration of Simulation

Long fabrication times in a wafer fab make the simulation of semiconductor fabrication processes and device behaviour an indispensable aid for experimenting with device designs and process parameters. vVhen a first prototype device leaves the fabrication facility, it is likely to be rejected due to a couple of possible flaws. Any deviation of the device parameters from the desired device specification causes modifications to be made to the device design and starts a new iteration of the outer design fabrication loop (ref. Fig. 1). Any difference exceeding the specified tolerances between the device design and the device actually produced or simulated calls for a modification of the process design and triggers the inner design loop anew.