We present a framework that verifies and maintains the consistency between the representations of the form, function and behavior of mechatronic devices. These three aspects of the device represent the geometry, the task, and the actions taken to realize the task, respectively (Pahl and Beitz, 1996). They evolve simultaneously through the design process. When the designer makes a change to one ...

In this paper, the design and implementation of a real-time traffic light control system based on Fieldprogrammable Gate Array (FPGA) technology is reported. The traffic light control system is designed with VHDL language. Its function was verified with simulation. After that, the VHDL design was downloaded to FPGA board hardware to verify its function in experiment. The designed traffic light ...

This paper addresses the problem of formally verifying VHDL descriptions. More precisely, we check the correctness of a VHDL architecture w.r.t. another architecture of the same entity. Both of them are translated into recursive functional forms, and the proof of their equivalence is realized by means of the Boyer-Moore theorem prover. Our methodology is illustrated by a signi cant example that...

VHDL models for neural networks for automatic test generation of gate level circuits are presented in this paper. A program converts a gate netlist to its equivalent neural model. A good circuit and faultable bad circuits will be generated. A VHDL test bench has been developed to apply the faults to the neural network bad circuit model, and report tests that are generated for each injected fault.

A known problem in the area of hardware/software codesign is the selection of the proper interface between the different parts of the design. This paper presents a technique which eases the selection by combining different synthesis techniques together with rapid prototyping. Application field of the technique is the design of communication systems where C and VHDL are generated from a specific...

In this paper, we enrich VHDL with new specification constructs intended for hardware verification. Using our extensions, total correctness properties may now be stated whereas only partial correctness can be expressed using the standard VHDL assert statement. All relevant properties can now be specified in such a way that the designer does not need to use formalisms like temporal logics. As th...

∗ This work is supported by National Project and Tsinghua Science Research Foundation. Abstract− In this paper, a visual VHDL integrated design environment VIDE for high level design is presented. In VIDE, there are several graphical and textual mixed design entry tools (VDES) and a graphical objectoriented debugger (VDBG). VDES consists of several diagram editors and a visual text editor, whil...

In this report, we present a top-down VHDL modeling technique which consists of two main modeling levels: speci cation level and functional level. We modeled a RISC Processor (RP) in order to demonstrate the feasibility and e ectiveness of this methodology. All models have been simulated on a SPARC 1 workstation using the ZYCAD VHDL simulator, version 1.0a. Experimental results show feasibility...

The ROCCC (Riverside Optimizing Configurable Computing Compiler) is an optimizing C-to-VHDL compiler used to compile routines written in a subset of C to an application-specific circuit on an FPGA. ROCCC incorporates several powerful parallelizing transformations targeted towards code generation for FPGAs and can achieve performance comparable to hand-coded VHDL. We have demonstrated speedups r...