It has recently been shown that a combined input and output queued (CIOQ) switch with a speed-up factor of 2 can exactly emulate an output-queued (OQ) switch. The main benefit of using a CIOQ switch is to reduce memory bandwidth requirement while providing quality of service (QoS) guarantee. The key component for exact emulation is a matching algorithm for bipartite graphs. For example, a CIOQ ...

Network-on-Chip (NoC) is the interconnection platform that answers the requirements of the modern on-Chip design. Small optimizations in NoC router architecture can show a significant improvement in the overall performance of NoC based systems. Power consumption, area overhead and the entire NoC performance is influenced by the router crossbar switch. This paper presents implementation of 10x10...

Rapid growth of Internet traffic causes a new challenge in the design of high-speed switches. One of main design issues for high-speed switches is a scalability problem. This paper proposes a scalable crossbar matrix (SCM) switch architecture, which consists of multiple crossbar switch units(XSU) with virtual output queues(VOQs) at the inputs and single-cell scheduling decomposition buffers(SDB...

ATM switch architectures based on deflection routing are here examined, described in terms of a general switch model and compared with regards to their internal operations. Their common feature is the availability of multiple I/O paths through a multistage unbuffered interconnection network where conflicts for the same interstage link are dealt with by deflecting packets onto the wrong path. Th...

Hybrid switch architecture with electronic buffering/processing and optical switching fabric is receiving a lot of attention as potential candidate for the design of highperformance and scalable switches/routers. However, the reconfiguration overhead of optical fabrics brings new challenges to system and scheduling algorithm design. For example, speedup is compulsory to make the switch stable; ...

The main objective of this paper, a bidirectional dc–dc converter with duel coupled inductor is proposed. In the boost mode, two capacitors are parallel charged and series discharged by the coupled inductor. Thus, high step-up voltage gain can be achieved with an appropriate duty ratio. The voltage stress on the main switch is reduced by a passive clamp circuit. Therefore, the low resistance RD...

In this preliminary work we give a geometric characterization of the time-optimal trajectories for piecewise affine bistable switch. Such hybrid models play major role in systems biology, as they can expressively account behaviors simple gene-regulatory networks. A key example these biological circuits is genetic toggle switch, which optimality state switch has not been studied to present day. ...

Switch equivalence for transformation systems has been successfully used in many domains for the analysis of concurrent behaviour. When using graph transformation as modelling framework for these systems, the concept of negative application conditions (NACs) is widely used – in particular for the specification of operational semantics. In this paper we show that switch equivalence can be improv...

An improved active snubber cell is proposed for ZVT-ZCT PWM DC-DC boost converter. Zero voltage transition (ZVT) turn on and zero current transition (ZCT) turn off is provided by this active snubber cell. There is no extra current or voltage stresses on the main switch. Also, zero current switching (ZCS) turn on ZCT turn off is provided for the auxiliary switch. Although there is no extra volta...

Performance analysis of an Asynchronous Transfer Mode (ATM) switch involves modeling the input traffic source, the switching mechanism, and the cell departure process. A main issue which determines the overall accuracy in performance evaluation of ATM switch, is the use of an appropriate probabilistic model to describe the cell departure process. Until now, little work has been done in the lite...