Optimal Placement and Sizing of Fault Current Limiter in a Real Network: a Case Study (TECHNICAL NOTE)

In this paper, the effect of number and fault current limiter(FCL) location has been investigated in order to have maximum reduction of short circuit current level in all buses in a real network. To do so, the faulty buses were identified in terms of short circuit current level by computing short circuits on the desired network. Then, while the fault current limit was modeled, its optimal location and amount for the greatest reduction in the fault current level of the whole critical buses was determined. Optimization computations have been done using the genetic algorithm and method of reducing the search space and all implementation stages of the proposed algorithm and reduction of search space has been conducted in DIgSILENT software using programming language DPL. The obtained results indicate the high efficiency of the proposed method in reducing the short circuit current level of faulty buses and simultaneous improving the power quality.