This paper might fairly be said to fall between three stools: the presentation and justification of a number of related computational methods associated with LFSR sequences, including finding the order, recurrence and general term; the exploration of tutorial examples and survey of applications; and a rigorous treatment of one topic, the recursive construction of the number wall, which we belie...

A desirable property of iterated cryptographic algorithms, such as stream ciphers or pseudo-random generators, is the lack short cycles. Many previously mentioned algorithms are based on use linear feedback shift registers (LFSR) and nonlinear (NLFSR) their combination. It currently known how to construct LFSR generate a bit sequence with maximum period, but there no knowledge in case NLFSR. Th...

The article discusses various options for constructing binary generators of pseudo-random numbers (PRN) based on the so-called generalized Galois and Fibonacci matrices. terms "Galois matrix" "Fibonacci are borrowed from theory cryptography, in which linear feedback shift registers (LFSR) PRN according to schemes widely used. matrix generate identical sequences as LFSR generators. transition cl...

LFSR’s are widely used in the BIST environment. In [1] a multiphase technique is proposed to reduce the data transitions (DTs) in both the LFSR and the circuit under test. However, its multiphase clock generator is implemented by a conventional Johnson counter with a complex control logic, which requires considerable area overhead and power dissipation. Also the employed dynamic demultiplexers ...

In this paper, we propose a new scheme for BuiltIn Test (BIT) that uses Multiple-polynomial Linear Feedback Shift Registers (MP-LFSR’s). The same MP-LFSR that generates random patterns to cover easy to test faults is loaded with seeds to generate deterministic vectors for difficult to test faults. The seeds are obtained by solving systems of linear equations involving the seed variables for the...

In this paper, we analyze the generalized self-shrinking generator newly proposed in [8]. Some properties of this generator are described and an equivalent definition is derived, after which two attacks are developed to evaluate its security. The first attack is an improved clock-guessing attack using short keystream with the filter function (vector G) known. The complexity of this attack is O(...

This paper has emphasis on the novel sequence generation for the hardwired built in self test (BIST) of static random access memory (SRAM). It reduces the testing time of SRAM by generating all the pattern sequence in less time. BIST is a design technique that allows a circuit to test itself. Linear feedback shift register (LFSR) was used for the sequence generation in the BIST but novel sequen...

In this paper we present a new reseeding technique for LFSR-based test pattern generation suitable for circuits with random-pattern resistant faults. Our technique eliminates the need of a ROM for storing the seeds since the LFSR jumps from a state to the required state (seed) by inverting the logic value of some of the bits of its next state. An eflcient algorithm for selecting reseeding point...