Several very large scale integrated (VLSI) devices which are not available in radiation hardened version are still required to be used in spacecraft systems. Thus these components need to be tested for highenergy heavy ion irradiation to find out their tolerance and suitability in specific space applications. This paper describes the high-energy heavy ion radiation testing of VLSI devices for s...

We have investigated the effects produced by exposing a Field Programmable Gate Array (FPGA) based on static RAM to an Ion Beam. Tested devices have been taken from FLEX10K family manufactured by Altera Corporation. These parts are commercial graded and not qualified for application in radioactive environments. A design based on mixed plain and Triple-Modular-Redundant (TMR) shift registers (SR...

Total ionizing dose (TID) effects and single event effects (SEE) in antifuse-, Flash-, and SRAM-based field programmable gate arrays (FPGAs) are reviewed. There is a brief discussion of the programmable element impact on the FPGA architecture. In the following sections, most radiation data are from antifuse-based FPGAs. The basic TID mechanisms are introduced and used to explain the anomalies i...

The fast growing VLSI industry demands new techniques for configuring the FPGA. When it comes to defence and space application the configuration of the FPGA becomes more crucial. When it is required to configure the FPGA automatically, the need arises of more sophisticated and fast techniques for reconfiguration of FPGA. In the space application, the effect of radiation changes the bit patterns...

A dedicated high-speed 18 Kbit static memory featuring synchronous mode, parity and dual port access has been designed and fabricated in a quarter micron 3 metals commercial CMOS technology. This SRAM has been designed to be a test vehicle to measure Single Event Upset (SEU) effects on a real circuit. The measurements have been performed at the cyclotron of Louvain-la-Neuve, Belgium, with a pro...

This paper proposes and investigates schemes for hardening the conventional CMOS cross-coupled DRAM sense amplifier to single event upset (SEU). These schemes, adapted from existing SRAM hardening techniques, are intended to harden the dynamic random access memory to bitline-mode errors during the sensing period. Simulation results indicate that a 9kΩ L-resistor hardening scheme provides greate...

A combined experimental/computational study of cooperativity between halogen-(XB) and hydrogen bonding (HB) is presented. Selenourea (SeU) has been chosen due to its ability to act at the same time as an XB acceptor toward I(CF2)5CF3 (I1) through the two lone pairs on the selenium atom, and as a HB donor to the benzoate anion through its two amino moieties. All equilibrium constants have been e...

The architecture and implementation of the LEON-FT processor is presented. LEON-FT is a fault-tolerant 32-bit processor based on the SPARC V8 instruction set. The processors tolerates transient SEU errors by using techniques such as TMR registers, on-chip EDAC, parity, pipeline restart, and forced cache miss. The first prototypes were manufactured on the Atmel ATC35 0.35 µm CMOS process, and su...

When exposed to an harsh environment in space, high atmosphere or even on earth, Integrated Circuits undergo soft errors. Among these events the most worrying is an electrical upset, so called Single Event Upset (SEU) evidenced in latches. We present here the circuit architecture of a new SEU hardened latch. The hardening is based on an integrated redundancy of the information and a high impeda...