A frequency agile multiplying injection-locked oscillator (MILO) suitable for fast power cycling was designed in 65nm GP CMOS. Edge detectors and multiple injection sites extend the lock range of the x4 multiplier to 36.3% of its free-running frequency. Lock range is further extended to 55.7% (2.3-4 GHz) by using 2 MILOs with adjacent lock ranges. Monitoring circuits identify the correct MILO a...

This paper presents an ultra-wide-range all-digital delaylocked loop (DLL). The proposed DLL uses a novel delay circuit which uses the transistor’s leakage current in advanced CMOS process to generate a very large propagation delay. Thus, the proposed DLL can operate at very low frequency with small chip area and low power consumption. The proposed DLL can operate from 600 kHz to 1.2GHz in the ...

ABSTRACT This paper presents a design of a high speed Comparator design using 65nm digital CMOS technology on Cadence Virtuoso Design Tool. The proposed FLASH ADC Design consists of fully differential topology. The first stage provides a Voltage Divider circuit and the second stage is Comparator Design having high sampling frequency tolerance, and the high efficient common drain circuit provide...

This paper presents a self-calibration circuit to correct the non-monotonic response in the cascading digitally controlled oscillator (DCO). The proposed calibration circuit can solve the non-monotonic problem when the coarse-tuning control code is changed. The proposed DCO implemented with a standard performance 65nm CMOS process can output frequency ranges from 58.7 MHz to 481.6 MHz. And the ...

This paper presents a programmable, energy-efficient and realtime object detection accelerator using deformable parts models (DPM), with 2x higher accuracy than traditional rigid body models. With 8 deformable parts detection, three methods are used to address the high computational complexity: classification pruning for 33x fewer parts classification, vector quantization for 15x memory size re...

Three dimensional (3D) integrated circuits (ICs) have the potential to significantly enhance VLSI chip performance, functionality and device packing density. Interconnects delay and signal integrity issues are critical in chip design. In this paper, we extend the idea of redundant via insertion of conventional 2D ICs and propose an approach for vias insertion/placement in 3D ICs to minimize the...

In this paper a new Gm-C active filter with auto-tuning loop based on PLL architecture in CMOS technology is presented. The auto-tuning loop of the proposed structure is represented by a PLL having the voltage controlled oscillator implemented with a replica of Gm-C filter in positive feedback connection. The loop sets the biasing of VCO such that the oscillation frequency provided by the loop ...

In this paper, a high-sensitivity low-cost power-aware Support Vector Machine (SVM) training and classification based system, is hardware implemented for neural seizure detection application. The accelerator algorithm, adopted in work, the sequential minimal optimization (SMO). System blocks are to achieve best trade-off between sensitivity consumption of area power. proposed system achieves 98...

For a massive yet sustainable Internet-of-Things, ultra-low power management and voltage regulation are required to operate the nodes on ambient energy harvesting (EH) while delivering the required supply voltages to the sensing, computing and communication blocks. Latest related results obtained in the electronic circuits and systems (ECS) group include indoor/outdoor solar EH power management...

A discrete-time mixing architecture for software defined radio receivers is proposed. It exploits 8x RF voltage oversampling followed by charge domain weighting to achieve 40dB 3rd and 5th harmonic rejection without channel bandwidth limitations. Also noise folding is reduced by 3dB. A zero-IF downconverter chip in 65nm CMOS can receive RF signals up to 900MHz, with NFmin=12dB, IIP3=11dBm at <2...