1. Definition. A PLL is a feedback system that includes a VCO, phase detector, and low pass filter within its loop. Its purpose is to force the VCO to replicate and track the frequency and phase at the input when in lock. The PLL is a control system allowing one oscillator to track with another. It is possible to have a phase offset between input and output, but when locked, the frequencies mus...

The All Digital Phase Locked Loop consists of full digital components which are used in advanced communication systems like frequency synthesizer, Carrier and clock recovery, modulator/demodulator etc. Hence the performance analysis of ADPLL becomes very necessary when designing these equipments. The ADPLL contains phase detector, loop filter and Digital controlled oscillator. The performance o...

The problem of robust phase-locked loop design has attracted attention for many years, particularly since the advent of the global positioning system. This paper proposes and demonstrates the use of a fuzzy PLL to estimate the time-varying phase of a sinusoidal signal. It is shown via simulation results that fuzzy PLL's offer performance comparable to analytically derived PLL's (e.g. Kalman fil...

In this paper, a new digital phase-locked loop (DPLL) is proposed based on finite impulse response (FIR) filters. The proposed DPLL is more robust to incorrect noise information than the existing DPLL using fixed gain. We show the effectiveness of the proposed DPLL via a numerical example.

Phase error dynamics of a conventional second order Digital Phase Locked Loop (DPLL) and that of a newly proposed modified second order DPLL (MSODPLL) have been studied using digital computers. Ranges of initial conditions leading to the phase locking condition were determined from computer simulation of both conventional and modified second order DPLL. Lyapunov exponents were also examined, fo...

This paper presents a methodology to determine all-digital phase-locked loop (ADPLL) circuit variables based on required design specifications, including output phase noise, fractional spur and locking time. An analytical model is developed to characterize the effects of different noise sources on ADPLL output phase noise and fractional spur. Applying the proposed noise model, circuit variables...

We investigate a non-coherent detection technique based on phase-locked loop (PLL) for wireless communication applications, with an emphasis on Digital Enhanced Cordless Telephone (DECT) system. Performance of the PLL receiver in additive white Gaussian noise (AWGN)'and interference-limited environments is simulated and compared to that of the "traditional" non-coherent receivers: limiter-discr...

Volume 2, Issue 2 March – April 2013 Page 306 Abstract—Now-a-days various Digital Signal Processing systems are implemented on a platform of programmable signal processors or on application specific VLSI chips. Coordinate Rotation Digital Computer (CORDIC) algorithm has turned out to be such kind of programmable signal processor. In recent times, it has been a widely researched topic in the fie...

Abstract— This paper presents a novel approach to obtain fast locking PLL by embedding a nonlinear element in the loop of PLL. The nonlinear element has a general parametric Taylor expansion. Using genetic algorithm (GA) we try to optimize the nonlinear element parameters. Embedding optimized nonlinear element in the loop shows enhancements in speed and stability of PLL. To evaluate the perform...