This paper describes the strategy followed for dimensioning the coefficient width of the adaptive filters (FFE, echo and NEXT Cancellers) in a Gigabit Ethernet PHY Silicon implementation. These filters account for an important part of the circuit area and power consumption. It is therefore critical to ensure that they are properly dimensioned.

The development of state-of-the-art wireless communication transceivers in semiconductor technology is a challenging process due to complexity and stringent requirements of modern communication standards such as IEEE 802.11n. This tutorial paper describes a complete design, verification, and performance characterization methodology that is tailored to the needs of the development of state-of-th...

This paper addresses complexity issues at algorithmic and architectural level of digital baseband receiver ASIC design for the standards GSM/GPRS/EDGE, in order to reduce power consumption and die area as desired for cellular applications. To this end, the hardware implementation of a channel shortening pre-filter combined with a delayed decision-feedback sequence estimator (DFSE) for channel e...

Managing Generic IP verification requires consideration of uncertainties & dynamic changes of standard & specification during project execution. Such scenario requires well defined process which needs to be followed throughout the project execution. A creative approach is required to make sure verification architecture is flexible enough to adapt majority of the run time changes enabling faster...

A technique to include virtual prototyping in the design cycle of complex digital modem ASICs is presented. It is innovating by using the same behavioral description for both the prototype as well as the final circuit implementation. Relating to verification of the design, this is a crucial benefit. The article discusses the prototyping mechanism by using the design of an upstream cable modem A...

The traditional dilemma for performing network simulations with analog circuits is the great difficulty of handling the connectivity in hardware. The main problem is that hardware-based connectivity must be built following predefined plasticity and connectivity rules, and that once the hardware is built, it is usually not possible to change its configuration. We show here an alternative system ...

Project: BANDIT ESPRIT 29260 Doc. Title: Intermediate design case report about noise coupling analysis and reduction methodology.

This paper summarizes the content and application of the SEED2002 project. SEED2002 is a university/industry collaboration to enhance and reform the education in the field of semi-custom/full-custom ASIC design at the universities of Mannheim, Heidelberg and Kaiserslautern, Germany. With this project Cadence Design Systems enables us to teach leading-edge ASIC design using their most innovative...

At-speed test has become a requirement in IC technologies below 180 nm. Unfortunately, test mode switching activity and IR-drop present special challenges to the successful application of structural atspeed tests. In this paper we characterize these problems on commercial ASICs in order to understand how to implement more effective solutions.