A method to perform diagnostic test generation in sequential circuits by modifying a conventional test generator is presented. The method utilizes circuit netlist modification along with a forced value at a primary input in the modified circuit. Techniques to reduce the computational effort for diagnostic test pattern generation in sequential circuits are also presented. Speed-up of the diagnos...

This article describes the Boolean satis ability method for generating test patterns for single stuck at faults in combinational circuits This new method generates test patterns in two steps First it constructs a formula expressing the Boolean di erence between the unfaulted and faulted circuits Second it applies a Boolean satis ability algorithm to the resulting formula This approach di ers fr...

In current thesis, two test pattern generation approaches based on genetic algorithms are presented. The, first algorithm is designed so that it allows direct comparison with random method. Comparative results show that genetic algorithm performs better on large circuits, in the last stage of test generation when much of search effort must be made in order to detect still undetected faults. Exp...

This paper presents new techniques for speeding up deterministic test pattern generation for VLSI circuits. These techniques improve the PODEM algorithm by reducing number of back-tracks with a low computational cost. This is achieved by nding more necessary signal line assignments, by detecting connicts earlier, and by avoiding unnecessary work during test generation. We have incorporated thes...

Pseudorandom built-in self test (BIST) generators have been widely utilized to test integrated circuit and systems. In this Project an accumulator-based-3 weight test pattern generation scheme is presented and proposed scheme generates set of test patterns with weights 0, 0.5 and 1. These accumulators are mostly found in current VLSI chips and that the scheme can be efficiently to drive the har...

Recently, Larrabee proposed a sequential test generation algorithm for combinational circuits based on boolean satisfiability and presented results on benchmark circuits in support of the viability of this approach. Parallel implementations of test generation algorithms are attractive in view of the known difficulty (NP-completeness) of the problem. In this paper we suggest parallel versions of...

By adding a few logic gates and one or two modeling flip-flops to the circuit under test (CUT), we create a detection or diagnostic automatic test pattern generation (ATPG) model of transition delay faults usable by a conventional single stuck-at fault test pattern generator. Given a transition delay fault pair, the diagnostic ATPG model can either find an exclusive test or prove the equivalenc...

This paper presents an implicit methodology that constrains a test pattern generator to identify test sequences which can be reproduced by cellular automata (CA). The so identiied CA can be synthesized as an autonomous-nite state machine and can be attached to the inputs of a circuit under test (e.g., a controller). In this way, the circuit under test preserves its integrity and its performance...

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We introduce a new Automatic Test Pattern Generation (ATPG) methodology for compact generation of test sets, to detect non-robustly testable path delay faults in combinational and fully enhanced scanned circuits. The proposed framework is non-enumerative with respect to the faults examined, and relies on the appropriate formulation and generation of functions that are used to derive the desired...