A new current-controlled oscillator (CCO) is presented which is suitable for use in low-voltage and lowpower designs. These features, and the low supply dependence of this CCO all stem from using a regenerative mechanism in its primitive delay cells. The circuit is designed and simulated in a 0.8um BiCMOS technology.

Low noise amplifier when simulated for system level configuration, the scattering matrix in general and scattering parameters in specific play vital role in performance of low noise amplifier for various frequency bands. In this paper the scattering parameter performance was analysed for S-band for recent process technologies available for CMOS and BiCMOS for IEEE 802.11 b/g.

We present the basic structure and performance of CML current mode full adders, that are used as Carry Save Adders (CSA) in combinatorial multipliers. A 1.2 μm BiCMOS technology is used for simulations but the schematic assumes a 2.5-V power supply. Compared with binary voltage mode CSAs, the multivalued current mode CSAs have chip area and power dissipation advantage, but speed disadvantage. T...

A Bang-Bang Clock-Data Recovery (CDR) for 10 Gb/s optical transmission systems is presented. A direct modulated architecture is used for the design. Its loop characteristics can be derived using an analogy to 61 theory. The circuit was produced and measured in a commercial 0.25μm BiCMOS technology with a transition frequency fT=70 GHz.

Copyright 2011 KIEEME. All rights reserved. This is an open-access article distributed under the terms of the Creative Commons Attribution Non-Commercial License (http://creativecommons.org/licenses/by-nc/3.0) which permits unrestricted noncommercial use, distribution, and reproduction in any medium, provided the original work is properly cited. High Performance Current-Mode DC-DC Boost Conver...

A power amplifier topology is presented that incorporates a feedback network around the active device that can be tuned for smalland large-signal circuit operation. The PA is fabricated in a 120-nm SiGe BiCMOS process and from 37-47 GHz. The PA achieves a saturated output power of 23 dBm and a peak PAE of 20% at 38 GHz.

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