We give a combinatorial description of the toric ideal invariants Cavender-Farris-Neyman model with molecular clock (CFN-MC) on rooted binary phylogenetic tree and prove results about polytope associated to this ideal. Key polyhedral structure include that number vertices is Fibonacci number, facets can be described using “cluster” underlying tree, volume equal an Euler zig-zag number. The CFN-...

Low power and robust circuitry are permanent hotspots in VLSI design. Adiabatic logic is one of potential breakthroughs for these goals. Especially, designing reliable clock tree is very significant for adiabatic logic due to four-phase clocked power required for pipelined data transmission in adiabatic system. In this paper, we present analysis of charging speed and clock types that influence ...

Phylogenetic trees can be rooted by a number of criteria. Here, we introduce a Bayesian method for inferring the root of a phylogenetic tree by using one of several criteria: the outgroup, molecular clock, and nonreversible model of DNA substitution. We perform simulation analyses to examine the relative ability of these three criteria to correctly identify the root of the tree. The outgroup an...

In this paper, we propose new approaches for solving the usefulskew tree (UST) routing problem [17]: Clock routing subject to general skew constraints. The clock layout synthesis engine of our UST algorithms is based on the deferred-merge embedding (DME) paradigm for zero-skew tree [5; 11 and bounded-skew tree [8; 21 routings; hence, the names UST/DME and Greedy-UST/DME for our algorithms. They...

" " 5 4.066284e-03 " " 4.3 Other CVIEW modules \range" is used to prepare these output les for viewing on a Tektronix 4015 terminal or for plotting on a laser printer. It arranges scale factors and generates labels for the graphic output, providing more appropriate auto-scaling than is done by raw graph(1). This facility is automatically invoked by using any CVIEW command line display option. T...

In this paper, we present a new low power scan-based BIST technique which can reduce the switching activity during test operation. The proposed low power /energy technique is based on a gated clock scheme for the scan path and the clock tree feeding the scan path.

distributing the clock signal on the chip in a manner such that it reaches all sinks at exactly the same point in time, a huge effort must be made. For example, the H-clock tree or B-Tree can achieve a low clock skew at the cost of many additional wires, which increases the chip size, cost and energy dissipation due to the capacitances that are created by thousands of parallel wires in the cloc...

Wireless sensor networks (WSNs) assume a collection of tiny sensing devices connected wirelessly and which are used to observe and monitor a variety of phenomena in the real physical world. Time synchronization is an important issue in wireless sensor networks. Many applications based on these WSNs assume local clocks need to be synchronized to a common view of clock at each sensor node. Some e...

We propose a Bayesian method for testing molecular clock hypotheses for use with aligned sequence data from multiple taxa. Our method utilizes a nonreversible nucleotide substitution model to avoid the necessity of specifying either a known tree relating the taxa or an outgroup for rooting the tree. We employ reversible jump Markov chain Monte Carlo to sample from the posterior distribution of ...