Integrated Circuit (IC) Technology is growing day by day to enhance the circuit performance and to increase the density for compact systems. Conventional CMOS technology is playing a vital role in digital computation for past four decades. But there are certain challenges in scaling the CMOS devices for the last few years. A novel technology “Quantum dot Cellular Automata (QCA)” has been identi...

This paper presents two highly integrated receiver circuits fabricated in InP heterojunction bipolar transistor (HBT) technology operating at up to 2.5 and 7.5 Gb/s, respectively. The first IC is a generic digital receiver circuit with CMOS-compatible outputs. It integrates monolithically an automatic-gain-control amplifier, a digital clock and data recovery circuit, and a 1 : 8 demultiplexer, ...

This paper deals with the design and performance analysis of a ring oscillator using CMOS 45nm technology process in Cadence virtuoso environment. The design of optimal Analog and Mixed Signal (AMS) very large scale integrated circuits (VLSI) is a challenging task for the integrated circuit(IC) designer. A Ring Oscillator is an active device which is made up of odd number of NOT gates and whose...

This paper uses a CAD methodology proposed by the authors to design a low-power 2ndorder ΣΔM. This modulator has been fabricated in a 0.7μm CMOS technology to be used as the front-end of an energy metering mixed-signal ASIC and features 16.4bit at a digital output rate of 9.6kHz with a power consumption of 1.71mW. It yields a value of the figure which is the smallest reported to now, thus demon...

The excessive power dissipation is a major obstacle against the further scaling and the enhancement of the integrated circuit technologies. Several new techniques for the design of low power and high performance integrated circuits are proposed in this dissertation. Particular emphasis is placed on suppressing the leakage currents while enhancing the reliability in deeply scaled nanometer CMOS ...

This paper uses a CAD methodology proposed by the authors to design a low-power 2ndorder Σ∆M. This modulator has been fabricated in a 0.7μm CMOS technology to be used as the front-end of an energy metering mixed-signal ASIC and features 16.4bit at a digital output rate of 9.6kHz with a power consumption of 1.71mW. It yields a value of the figure which is the smallest reported to now, thus demon...

The high cost of IC design has made chip protection one of the first priorities of the semiconductor industry. Although there is a common impression that combinational circuits must be designed without any cycles, circuits with cycles can be combinational as well. Such cyclic circuits can be used to reliably lock ICs. Moreover, since memristor is compatible with CMOS structure, it is possible t...

As the operating supply voltage for commercial CMOS devices falls below 2 V, research activities are underway to develop CMOS integrated circuits that can operate at supply voltages well under 1 V. Although dramatic power reductions can be achieved using low supply voltages in high performance applications, the increased subthreshold leakage that results when transistor threshold voltages are l...

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