Rapid Single Flux Quantum (RSFQ) logic is a promising technology to supersede Complementary metal-oxidesemiconductor (CMOS) in some specialized areas due providing ultra-fast and energy-efficient circuits. To realize large-scale integration design, electronic design automation (EDA) tools for RSFQ are required the divergences type, timing constraints, circuit structure compared with CMOS logic....

Reversible circuit designing is the area where researchers are focussing more and more for the generation of low loss digital system designs. Researchers are using the concept of Reversible Logic in many areas such as Nanotechnology, low loss computing, optical computing, low power CMOS design etc. Here we have proposed a novel design approach for a 2-bit binary Arithmetic Logic Unit (ALU) usin...

This paper qualitatively explores the performance limits, i.e., energy vs. frequency, of adiabatic logic circuits based on nanoelectromechanical (NEM) switches. It is shown that the contact resistance and the electro-mechanical switching behavior of the NEM switches dictate the performance of such circuits. Simplified analytical expressions are derived based on a 1-dimensional reduced order mod...

In this paper, a test circuit for a test method is proposed, with which open leads of CMOS logic ICs are detected without generating test input vectors. Open leads are detected by means of supply current of the test circuit that flows when an AC voltage signal is provided to targeted leads with test probes as a stimulus. It is examined by some experiments whether open leads will be detected wit...

A new Quasi-Static Energy Recovery Logic family (QSERL) using the principle of adiabatic switching is proposed in this paper. Most of the previously proposed adiabatic logic are dynamic and require complex clocking schemes. The proposed Quasi-Static energy recovery logic uses two complementary sinusoidal supply clocks and resembles behaviors of static CMOS. Thus, switching activity is signiican...

CMOS was developed as a digitally friendly process. Now, thanks to high levels of system integration and the emergence of SOC (system-on-chip) design, CMOS has also become the process of choice for mixed-signal applications. However, cutting-edge CMOS has limitations in these applications. Process restrictions, inaccurate simulation models, wide parametric variance, and noisy application enviro...

Abstract In this paper we propose a new compact static delay model for latch-based CMOS Threshold logic gates. The particular effects captured by the model are: the dependency of the delay on threshold (data) values and the dependency of the delay vs. capacitive loading. The model parameters were extracted from several Threshold logic gate setups and the delay predicted by the model for a compu...

In this paper, footless domino logic buffer circuit is proposed. It minimizes redundant switching at the dynamic and the output nodes. This circuit passes propagation of precharge pulse to the dynamic node and avoids precharge pulse to the output node which saves power consumption. Simulation is done using 0. 18μm CMOS technology. We have calculated the power consumption, delay and power delay ...

A novel low power and Positive Feedback Adiabatic Logic (PFAL) combinational low power circuit is presented in this paper. The power consumption and general characteristics of the PFAL combinationallow power circuit arethen compared against two combinational low power circuit Efficient Charge Recovery Logic (ECRL), Conventional CMOS. The proposed PFAL combinational low power circuit design was ...

As CMOS scaling options are exhausted by fundamental limitations, device and circuit integration in the third-dimension could provide a possible pathway without extensively relying on ultra-scaled transistors. So far, however, the migration of CMOS to 3-D has been unattainable. The CMOS fabric architecture uses complementary MOSFETs in an inverted logic, where both pull-up and pull-down transis...