Instruction scheduling and register allocation are two very In this paper, we solve register allocation and instruction scheduling simultaneously using integer linear programming (ILP). theform ulation?a new ???v ariableU has taken several approaches, including: branch-andbound enumeration (5) (13). more expensive register spill and reload instructions in the program. Eager code This thesis dev...

The paper presents a novel static algorithm for mapping values to multiple register files. The algorithm is based on the edge-coloring of a bipartite graph. It allows the migration of values among the register files to keep the number of RAMs as small as possible. By comparison with the register file design used in the Cydra 5 mini-supercomputer, our approach substantially reduces the number of...

There exist extensive ongoing research efforts on emerging technologies that have the potential to become an alternative to today’s CMOS technologies. A common feature among the investigated technologies is that of multivalue devices and the possibility of implementing quaternary logic and memory. However, multi-value devices tend to be more sensitive to interferences and, thus, have reduced er...

In this paper, a low power register file and tag comparator is proposed which has lower leakage and higher noise immunity without dramatic speed degradation due to the wide fan-in gates. Simulation of register files and tag comparators designed is done using low-Vth 90 nm CMOS process technology model in all process corners. The results demonstrate 20% power reduction and 2 noise-immunity impro...

In this paper, we present an extension of active automata learning to register automata, an automaton model which is capable of expressing the influence of data on control flow. Register automata operate on an infinite data domain, whose values can be assigned to registers and compared for equality. Our active learning algorithm is unique in that it directly infers the effect of data values on ...

The Single Instruction, Multiple Data (SIMD) execution model has been receiving renewed attention recently. This awareness stems from the rise of graphics processing units (GPUs) as a powerful alternative for parallel computing. Many compiler optimizations have been recently proposed for this hardware, but register allocation is a field yet to be explored. In this context, this paper describes ...

The introduction of FinFET technology has turned DRAMs into an interesting candidate to substitute traditional SRAM-based on-chip memory structures (i.e. register file, cache memories). Nevertheless, a major problem to introduce these cells is that they lose their state (i.e. value) over time, and they have to be refreshed. This paper is the first one to propose the implementation of coherent c...

This paper deals with the numerical solution of financial applications, more specifically the computation of American option derivatives modelled by nonlinear boundary values problems. In such applications we have to solve largescale algebraic systems. We concentrate on synchronous and asynchronous parallel iterative algorithms carried out on CPU and GPU networks. The properties of the operator...

The paper presents a novel static algorithm for mapping values to multiple register les. The algorithm is based on the edge-coloring of a bipartite graph. It allows the migration of values among the register les to keep the number of RAMs as small as possible. By comparison with the register le design used in the Cydra 5 mini-supercomputer, our approach substantially reduces the number of RAMs....

Two hundred fifty five medial prefrontal cortical (MPFC) and 187 caudate-putamen (CPu) sites were evaluated for intracranial self-stimulation in 67 animals using moveable electrodes and collecting trade-off functions between current and frequency. Eleven percent of the examined areas, located predominantly in the ventromedial aspects of MPFC and CPu, showed reliable self-stimulation and the ave...