Designing of modern digital circuits require high performance with reduced cost and minimal time to market. In order to achieve greater performance, timing analysis is done to meet all the timing constraints. It also leads to increase the complexity of emerging Very Large Scale Integration (VLSI) design. Timing analysis eliminates the occurrence of non-functional path. In this work, path tracin...

We present Parkour, a tool that creates parallel speedup estimates for unparallelized serial programs. Unlike previous approaches, it does not require any prior human analysis or modification of the program. Parkour automatically quantifies the parallelism of a given program and provides an approximate upper bound for performance, modeling fundamental parallelization constraints. For the evalua...

In this paper we introduce a new approach to fault simulation, using reconfigurable hardware to implement a critical path tracing algorithm. Our performance estimate shows that our approach is at least on order of magnitude faster than serial fault emulation used in prior work.

Implementation of wireless wideband transmitters using ∆Σ DACs requires very high speed modulators. Digital MASH ∆Σ modulators are good candidates for speed enhancement using interleaving because they require only adders and can be cascaded. This paper presents an analysis of the integrator critical path of two-channel interleaved ∆Σ modulators. The bottlenecks for a high-speed operation are id...

An activity network is an acyclic graph with non-negative weights and with a unique source and destination. A project consisting of a set of activities and precedence relationships can be represented by an activity network and the mathematical analysis of the network provides useful information for managing the project. In a traditional activity network, it is assumed that an activity always be...

The ability to predict the performance of a simulationapplication before its implementation is an important factor to the adoption of parallel simulation technology in industry. Ideally, a simulationist estimates the inherent parallelism of a simulation problem to determine whether it is worthwhile to invest resources to carry out a parallel simulation. In this paper, we proposed an analytic me...

A full digital self-timed clock generation scheme is developed, where multiple internal clocks are self-generated for each external request. The internal clock period is designed to be the critical path delay of the internal system at all operating environments. This scheme can be applied to time-multiplexed implementations, self-timed operation , and low-power applications.