due to the expected increase of defects in circuits based on deep submicron technologies, reliability has become an important design criterion. although different approaches have been developed to estimate reliability in digital circuits and some measuring concepts have been separately presented to reveal the quality of analog circuit reliability in the literature, there is a gap to estimate re...

Reliability of nanodevices is expected to be a central issue with the advent of very-deep submicon devices and future single-electron transistors. We propose a new approach based on the assumption that a number of circuit-level devices are to be expected to fail. Artificial neural networks can be trained to resists to errors and be used for synthesizing fault-tolerant Boolean functions. The dev...

During the past few years, a lot of work has been done on behavioral models and simulation tools. But a need for modeling strategy still remains. The VHDL-AMS language supports the description of analog electronic circuits using Ordinary Differential Algebraic Equations (ODAEs), in addition to its support for describing discrete-event systems. For VHDL-AMS to be useful to the analog design ...

in this work, a simple and effective way to modify the support surface is developed and a nanostructure ceramic support to facilitate deposition of a defect-free overlying micro and meso (nano) porous membrane is obtained. to achieve high performance nanocomposite membranes, average pore size of outer surface of support was reduced by dip-coating in submicron and nano α-alumina slurries. in thi...

As technology scales into the deep submicron regime, noise immunity is becoming a metric of comparable importance to area, timing, and power for the analysis and design of very large scale integrated (VLSI) systems. A metric for noise immunity is defined, and a static noise analysis methodology based on this noise-stability metric is introduced to demonstrate how noise can be analyzed systemati...

To certify the correctness of a design, in deep submicron technologies, the verification process has to cover some new issues. The noise introduced on signals through the crosstalk coupling is one of these emerging problems. In this paper, we propose a model to evaluate the peak value of the noise injected on a signal during the transition of its neighboring signals. This model has been used in...

Today’s ASIC designs consist of more memory in terms of both area and number of instances. The shrinking of geometries has an even greater effect upon memories due to their tight layouts. These two trends are putting much greater demands upon memory BIST requirements. At-speed testing and custom test algorithms are becoming essential for insuring overall product quality. At-speed testing on mem...

Placement of multiple dies on an MCM or high-performance VLSI substrate is a non-trivial task in which multiple criteria need to be considered simultaneously to obtain a true multi-objective optimization. Unfortunately, the exact physical attributes of a design are not known in the placement step until the entire design process is carried out. When the performance issues are considered, crossta...