Delay locked loops are an attractive alternative to VCO based phase locked loops due to their simpler design and inherent stability [1]-[3]. The primary disadvantage of conventional DLLs is their limited phase range, which limits their application to mesochronous environments. This dual DLL architecture combines several techniques to achieve unlimited phase shift, low jitter and large operating...

This paper designed a tapped delay line Time-to-Digital Converter(TDC) based on 0.18μm CMOS, there is total level 128 voltage-controlled delay line.The symmetric delay phase-locked loop is used to increase the stability of delay chain and reduce the system clock’s skew and jitter. The simulation results show that : when the voltage is 1.8V, and the reference clock frequency is 250MHz, the least...

Abstract: This paper describes the architecture and performance of a high-resolution time–to– digital converter (TDC) based on a Vernier delay line. The TDC is used as a basic building block for time interval measurement in an ultrasonic liquid flowmeter. Operation of the TDC with 10ps LSB resolution and 1 ms input range has been simulated using library models for 1.2 μm double–metal double–pol...

The grid frequency estimation using a recursive signal or an integrator-based method may suffer from stability issue due to accumulation discretization error. To avoid these shortcomings and also obtain robust of three-phase under unbalanced distorted conditions, this letter proposes demodulation-based without integrator. proposed approach relies on the Clarke transform fixed transport delay-ba...

In this paper, the modern nonlinear theory is applied to a third order phase locked loop (PLL) with feedback time delay. Due delay, different behaviors that are not accounted for in conventional PLL model identified, namely, oscillatory instability, periodic doubling and chaos. Firstly, Pade approximation used delay where it utilized deriving state space representation of under investigation. T...

In this paper, we propose a new algorithm for the detection of howling signal employing LMS adaptive notch filter and digital phase locked loop. The main advantages of the proposed algorithm are that it has very low computational complexity and has a short detection delay. Computer simulations are given to demonstrate the performance of this method.

We have developed a wideband phase-locked loop (PLL) circuit with real-time phase correction for high-speed and accurate force measurements by frequency modulation atomic force microscopy (FM-AFM) in liquid. A high-speed operation of FM-AFM requires the use of a high frequency cantilever which, however, increases frequency-dependent phase delay caused by the signal delay within the cantilever e...

PN code tracking is one of the most important factors that affect the performance of spread spectrum receivers. It is desirable to maintain PN code tracking for a long period of time and with high accuracy. This paper presents a non-coherent digital delay-locked loop (DLL) for code tracking in direct-sequence spread spectrum (DS-SS) systems. The proposed technique utilizes three non-coherent co...

time-delay identification is one of the most important parameters in designing controllers. in the cases where the number of inputs and outputs in a system are more than one, this identification is of great concern. in this paper, a novel autocorrelation-based scheme for the state variable time-delay identification for multi-input multi-output (mimo) system has been presented. this method is ba...