In this paper a new phase-frequency detector is proposed using transmission gates which can detect phase difference less than 500ps. In other word, the proposed Phase-frequency Detector (PFD) can work in frequencies higher than 1.7 GHz, whereas a conventional PFD operates at frequencies less than 1.1 GHz. This new architecture is designed in TSMC 0.13um CMOS Technology. Also, the proposed PFD a...

The achievable off-chip bandwidth of digital IC's is a crucial and often limiting factor in the performance of digital systems. In intra-system interfaces where both latency and bandwidth are important, source-synchronous parallel channels have been adopted as the most effective solution. This work investigates receiver and clocking circuit design techniques for increasing the signalling rate a...

Irregularities in the Earth's ionosphere can make the amplitude and phase of radio signals fluctuate rapidly, which is known as ionospheric scintillation. Severe ionospheric scintillation could affect the performance of the Global Navigation Satellite System (GNSS). Currently, the Multiple Phase Screen (MPS) technique is widely used in solving problems caused by weak and strong scintillations. ...

This article describes a dual-controller dual-delay line delay lock loop (DC-DL DLL). The proposed DLL adopted dual structure, each was composed of coarse adjustment and fine unit, the lines had corresponding control units to reduce mismatch between lines, it avoided complicated design duty cycle correction (DCC) circuit. A frequency divider added divide input clock achieve wider adjustment. Ad...

In this chapter we discuss flexible cognitive radio circuits for dynamic access of unused spectrum. Ideally, such circuits can work at an arbitrary radio frequency (RF). We review techniques to realize radios without resorting to frequency selective dedicated filters [24], in particular a recently proposed polyphase multipath technique canceling harmonics and sidebands [11,12]. Using this techn...

This work aimed at investigating the performances of different discriminators used in a Delay Lock Loop (DLL) in a multipath environment. A filter based on rake receiver module is proposed to overcome the distorsions caused by reflected rays of the incoming signal. Experimental results confirm the effectiveness of the proposed method.

The duty-cycle of a clock, within the VLSI IC, is liable to be changed when the clock passes through several buffer stages in the multistage clock buffer design. The pulse-width may be changed due to unbalance of the p and n MOS transistors in the long CMOS buffer. This paper describes a delay locked loop with double edge synchronization mainly used in a clock alignment process. SPICE simulatio...

This paper is a review of methods and techniques used for precise measurement of time intervals (TIs) or precise conversion of TIs to digital data. The following methods are described: the counter method and averaging, time stretching, time-to-amplitude conversion followed by analogue-to-digital conversion, the Vernier method, conversion utilizing tapped delay lines, and interpolation methods. ...

This paper presents a digitally programmable delay line intended for use as timing generator in a RADAR ranging system. Traditional delay lines are realized selecting the delayed signal from a tap in a cascade of delay elements, resulting in a delay resolution limited by the matching errors between the delay elements. The architecture of the programmable delay line presented in this paper uses ...

the aim of this paper is to minimize output phase noise for the pure signal synthesis in the frequency synthesizers. for this purpose, first, an exact mathematical model of phase locked loop (pll) based frequency synthesizer is described and analyzed. then, an exact closed-form formula in terms of synthesizer bandwidth and total output phase noise is extracted. based on this formula, the phase ...