This paper presents high speed and low power full adder cells designed with an alternative internal logic structure and Gate Diffusion Input (GDI) logic styles and hybrid CMOS logic style that lead to have a reduced Power Delay Product (PDP). The main design objective for this adder module is not only providing low-power dissipation and high speed but also full-voltage swing. In the first desig...

Full adder is the functional building block and basic component in several architectures found in VLSI and DSP applications, Adder is a versatile component and mainly used in addition and multiplication as the basic processing element; Adder in a VLSI application is used in ALU design, Address generation in processors, Multipliers and so on. In DSP applications it is used code for conversion, S...

Floating Point (FP) arithmetic is widely used in large set of scientific and signal processing computation. Adder/subtractor is one of the common arithmetic operation in these computation. The design of FP adder/subtractor is relatively complex than other FP arithmetic operations. This paper has shown an efficient implementation of adder/subtractor module on a reconfigurable platform, which is ...

application of quantum-dot is a promising technology for implementing digital systems at nano-scale.  quantum-dot cellular automata (qca) is a system with low power consumption and a potentially high density and regularity. also, qca supports the new devices with nanotechnology architecture. this technique works based on electron interactions inside quantum-dots leading to emergence of quantum ...

We present the design of a quantum carry-lookahead adder using measurement-based quantum computation. The quantum carry-lookahead adder (QCLA) is faster than a quantum ripple-carry adder; QCLA has logarithmic depth while ripple adders have linear depth. Our design is evaluated in terms of number of time steps and the total number of qubits used.

In this paper, five new multiplexer-based architectures for 1 -bit full adder circuit designs are proposed. Following these architectures, various full adder circuits can be built through different circuit implementations of multiplexers. For instance, in this paper, we demonstrate that by substituting each multiplexer with two transmission gates, a set of new full adder circuits are ready to b...

ÐResidue number system (RNS) arithmetic has a promising role for fault-tolerant high throughput superconducting single ̄ux quantum (SFQ) circuits for digital signal processing (DSP) applications. We have designed one of the basic computational blocks used in DSP circuits, one-decimaldigit RNS adder. A new design for its main component, the single-modulus adder, has been developed. It combines s...

Carry Select Adder (CSLA) which provides one of the fastest adding performance. Traditional CSLA require large area and more power. Recently a new CSLA adder has been proposed which performs fast addition, while maintaining low power consumption and less area. This work mainly focuses on implementing the 128 bit low power and area efficient carry select adder using 0.18 μm CMOS technology. Base...