We developed a double-recess etching process and a new Digital-Oxide-Deposition (DOD) technique to fabricate 180nm low-threshold GaN Metal-OxideSemiconductor Double Heterostructure Field Effect Transistors (MOS-DHFET). Two device layer structures, InGaN channel design and InGaN back-barrier design, were employed to improve the confinement of TwoDimensional Electron Gas (2DEG) and mitigate the s...

Though silicon tunnel field effect transistor (TFET) has attracted attention for sub-60mV/decade subthreshold swing and very small OFF current (IOFF), its practical application is questionable due to low ON current (ION) and complicated fabrication process steps. In this paper, a new n-type classical-MOSFET-alike tunnel FET architecture is proposed, which offers sub-60mV/decade subthreshold swi...

Nanosheet Field Effect Transistor (NSFET) is a viable contender for future scaling in sub-7-nm technology. This paper provides insights into the variations of DC FOMs different geometrical configurations NSFET. In this script, performance 3D GAA NSFET analyzed by varying device's width and thickness. Moreover, gate length scaled from 20 nm to 5 check device suitability continuous logic applicat...

Since at the regime of nanometer, quantum confinement effects are observed and wave nature electrons is more dominant. Therefore, classical approach current formulation in mesoelectonics nanoelectronics results inaccuracy as it does not consider effect, which only applicable for bulk electronic device. For accurate modeling simulation nanoelectronics, device atomic-level mechanical models requi...

A gate-controlled metal-semiconductor barrier modulation and its effect on carrier transport were investigated in two-dimensional (2D) transition metal dichalcogenide (TMDC) field effect transistors (FETs). A strong photoresponse was observed in both unipolar MoS2 and ambipolar WSe2 FETs (i) at the high drain voltage due to a high electric field along the channel for separating photo-excited ch...

This letter demonstrates a p-type raised source-and-drain (raised S/D) junctionless thin-film transistors (JL-TFTs) with a dual-gate structure. The raised S/D structure provides a high saturation current (>1 μA/μm). The subthreshold swing (SS) is 100 mV/decade and the drain-induced barrier lowering (DIBL) is 0.8 mV/V, and the I on/I off current ratio is over 10(8) A/A for L g = 1 μm. Using a th...

To extend the use of CMOS technology beyond 14 nm node technology, new device materials are required that can enhance the performance of MOSFETs. The use of high-k materials in double gate (DG) MOSFET can triumph over the problem of power dissipation and leakage current. In this paper, we investigated various high-k dielectrics as the gate oxides in a 12 nm SOI FinFET and the performance potent...

In this paper we look at the quantitative picture of fringing field efSects by use of high-k dielectrics on the 70 nm node CMOS technologies. By using Monte-Carlo based techniques, we extract the degradation in gate-to-channel capacitance and the internal, external fringing capacitance components for varying values of K. Our results clearly show the decrease in external fringing capacitance, in...