The trade-offs between bandwidth, resolution and power in high dynamic range pipeline analog-to-digital converters are studied when a pure digital CMOS technology is considered. Calibration techniques are presented to achieve the required resolution, and the design optimization methodology of the relevant pipeline building blocks are discussed. An example of a 15-b 10Ms/s analog-to-digital pipe...

Very long-running queries in database systems are not uncommon in non-traditional application domains such as image processing or data warehousing analysis. Query optimization, therefore, is important. However, estimates of the query characteristics before query execution are usually inaccurate. Further, system conngu-ration and resource availability may change during long evaluation period. As...

The paper is devoted to the study of an algorithm for optimization of inhibitory rules relative to the length. Such rules on the right-hand side have a relation "attribute value". The considered algorithm is based on an extension of dynamic programming. After the procedure of optimization relative to length, we obtain a graph (T) which describes all nonredundant inhibitory rules with minimum le...

The advancement in CMOS technology has surpassed the progress in computer aided design tools, creating an avenue for new design optimization flows. This paper presents a design level transistor sizing based timing optimization algorithms for mixed-static-dynamic CMOS logic designs. This optimization algorithm performs timing optimization through partitioning a design into static and dynamic cir...

Bayesian optimization (BO) algorithms try to optimize an unknown function that is expensive to evaluate using minimum number of evaluations/experiments. Most of the proposed algorithms in BO are sequential, where only one experiment is selected at each iteration. This method can be time inefficient when each experiment takes a long time and more than one experiment can be ran concurrently. On t...