The necessary and sufficient conditions for detecting transistor stuck-open faults in arbitrary multi-level;el CMOS circuits are show. A method for representing a twopattern test for detecting a single stud-open fault using only one cube is presented. The relationship between the D-algorithm and the conditions for detecting transistor stuck-open faults in CMOS circuits is provided. The applicat...

This paper describes initial work towards building an explicit assurance case for DO-178C / ED-12C. Two specific questions are explored: (1) What are some of the assumptions upon which the guidance in the document relies, and (2) What claims are made concerning test coverage analysis?

In this paper, we present a fast and efficient algorithm for BISTing datapaths described at the Register Transfer (RT) level. This algorithm is parameterized by user defined tuning factors allowing tradeoffs between fault coverage, area overhead and test application time. This algorithm is also generic i.e. independent of the test pattern generators and compactors types.

A fault coverage evaluation concerning a linked neighborhood pattern sensitive faults model (NPSFs) in N × 1 random-access memories is presented. For the simulation study, the most important published tests dedicated to the NPSF model have been considered. Simulation results show that these tests cover the entire model of simple NPSFs, but only the longer of them cover the linked NPSF model. In...

The purpose of this paper is to propose a new histogram-based diflerential current testing procedure of active defects. This procedure contains three steps: Preanalysis, Failure Analysis, and Production Testing. The main objehtives of the Pre-analysis are to provide information on the most frequent active current defects and to help ‘setting the limits between faulty and fault-free devices: the...

This paper presents an analysis of the fault coverage provided by the UIO-based methods for testing communications protocols. Formal analysis of the fault coverage for the non-optimized method and for some of its optimized versions are presented. A test is said to provide full coverage if no erroneous implementation can pass the test. In the case of optimizations based on the Rural Chinese Post...

In this paper, we employ the Communicating finite state machine (CFSM) model for networks to investigate fault management using passive testing. First, we introduce the concept of passive testing. Then, we introduce the CFSM model and the observer model with necessary assumptions and justification. We introduce the fault model and the fault detection algorithm using passive testing. We present ...

Delay faults are an increasingly important test challenge. Traditional delay fault models are incomplete in that they only model a subset of delay defect behaviors. To solve this problem a combined delay fault (CDF) model has been developed, which models delay faults caused by the combination of spot defects, parametric process variation, and capacitive coupling. The spot defects are modeled as...

This paper presents an efficient scheme to improve the test generation of voltage testing under the competing bridge fault model. A procedure is presented that extracts test generation objectives from switch-level networks, which will maximize the likelihood of detecting a bridging fault that is undetectable by a stuck-at test set. The effects of both active feedback and variations in transisto...

Testing applications involves the creation of test sets, their execution, management and adequacy assessment. An extensible framework, called RiOT, has been developed to allow the implementation of tools for test coverage measurement, test execution management and fault-based testing of distributed Java applications. Test coverage is measured in terms of elements covered in the interface descri...