devices necessitate evaluating the SEU mechanisms of FinFET circuit stability at low supply voltages dissipation, it is also necessary over a range of voltages. FinFET proton exponential low simulations show that the weak variation of supply voltage critical charge Index Terms particles, Neutrons, Heavy The Semiconductor Industry Association (SIA) roadmap has identified power dissipation as one...

As CMOS electronic devices are continuously shrinking to nanometer regime, leads to increasing the consequences of short channel effects and variability due to the process parameters which lead to cause the reliability of the circuit as well as performance. To solve these issues of CMOS, FINFET is one of the promising and better technologies without sacrificing reliability and performance for i...

Scaling of single-gate MOSFET faces great challenges in the nanometer regime due to the severe shortchannel effects that cause an exponential increase in the sub-threshold and gate-oxide leakage currents. Double-gate FinFET technology mitigates these limitations by the excellent control over a thin silicon body by two electrically coupled gates. In this paper a variable threshold voltage keeper...

The effect of gate – drain/source underlap (Lun) on a narrow band LNA performance has been studied, in 30 nm FinFET using device and mixed mode simulations. Studies are sssssdone by maintaining and not maintaining the leakage current (Ioff) and threshold voltage (Vth) of the various devices. LNA circuit with two transistors in a cascode arrangement is constructed and the input impedance, gain a...

This paper describes the characteristics comparison of bulk FINFET and SOI FINFET. The scaling trend in device dimension require limit on short channel effect through the control of subthreshold slope and DIBL characteristics.It can be achieved by proper device design. The subthreshold characteristics are plotted with the variation of gate voltage for different doping profile .This paper also c...

High performance PMOSFETs with a gate length as short as 18-nm are reported. A self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short channel effect. The 45 nm gate-length PMOS FinFET has an Idsat of 410 PA/Pm (or 820 PA/Pm depending on the definition of the width of a double-gate device) at Vd = Vg = 1.2 V and Tox = 2.5 nm. The quasi-planar nature of this variant of t...