This work presents a methodology to analyze aging effects in different flip-flops topologies. As CMOS transistor scaling to nanometer technologies in the last decades, new issues have become major concerns in VLSI design. One of those new issues is aging. Aging effects impact on performance and reliability of CMOS circuits. Flip-flops are one of the main structures in VLSI circuits. Their chara...

Abstract We discuss the symplectic topology of Stein manifolds obtained by plumbing two 3-dimensional spheres along a circle. These spaces are related, at derived level and working in characteristic determined specific geometry, to local threefolds which contain floppable $$(-1,-1)$$ ( - <mml:...

In Integrated circuits a gargantuan portion of on chip power is expended by clocking systems, which comprises of timing elements such as flip-flops, latches and clock distribution network. These elements absorb approximately 30% to 60% of the total power dissipation in the system. In order to design high performance and power efficient circuits a scrupulous approach should be adopted to reduce ...

Energy recovery clocking has been demonstrated as an effective method for reducing the clock power. However, in this method the conventional square wave clock signal is replaced by a sinusoidal clock generated by a resonant circuit. Such a modification in clock signal prevents application of existing clock gating solutions. In this paper, we propose clock gating solutions for energy recovery cl...

Flip-Flops are off many types. Choosing the correct type FF for any application is very important to achieve high performance. the data look ahead d Flip-Flop (DLDFF) from the family of master-slave type is compared with pulse triggered conditional capture Flip-Flop(CCFF).The effect of clock gating on the performance of these Flip-Flops are analyzed. The two Flip-Flops are compared, with clock ...

A UART (Universal Asynchronous Receiver and Transmitter) is a device allowing the reception and transmission of information, in a serial and asynchronous way. This project focuses on the implementation of UART with status register using multi bit flip-flop and comparing it with UART with status register using single bit flip-flops. During the reception of data, status register indicates parity ...

In this paper, the proposed flip-flop reduces power consumption by reducing the clock switching power that was wasted otherwise. Unlike many other gated flip-flops, the proposed gated flip-flop has state retention property to save power and to switch circuit between idle and active modes smoothly. The feedback path is also improved in the proposed flip-flop to decrease power dissipation. The pr...