This paper describes methods for synthesizing the internal representation of a compiler into a hardware description language in order to program reconfigurable hardware devices. We demonstrate the usefulness of static single assignment (SSA) in reducing the amount of data communication in the hardware. However, the placement of Φ-nodes by current SSA algorithms is not optimal in terms of minimi...

In this paper, the electrical performance of double gate organic field effecttransistor (DG-OFET) are thoroughly investigated and feasibility of the deviceas an efficient biosensor is comprehensively assessed. The introduced deviceprovides better gate control over the channel, yielding better charge injectionproperties from source to channel and providing higher on-state...

in advance longwall mining, the safety of mine network, production rate, and consequently, economic conditions of a mine are dependent on the stability conditions of gate roadways. the gate roadway stability is a function of two important factors: 1) characteristics of the excavation damaged zone (edz) above the gate roadway and 2) loading effect due to the caving zone (cz) above the longwall w...

ECCGen is a logic synthesizer for error control coding circuits. It takes H matrices as inputs and produces circuit schematics in two steps, literal minimization and gate/pin assignment. Di erent from conventional logic synthesis tools, it takes a structural approach to avoid the combinatorial explosion problem in Boolean function and/or true table representations of ECC circuits. Moreover, the...

We describe a new synthesis procedure for designing asynchronous controllers from burst-mode specifications, a class of specifications allowing multiple input change fundamental mode operation. Our implementation of burst-mode state machines uses standard combinational logic, generates low-latency outputs and guarantees freedom from hazards at the gate level. It requires no locally-synthesized ...

This paper presents a satisfiability-based method for solving the board-level multiterminal net routing problem in the digital design of clos-folded field-programmable gate array (FPGA) based logic emulation systems. The approach transforms the FPGA board-level routing task into a Boolean equation. Any assignment of input variables that satisfies the equation specifies a valid routing. We use t...

This paper presents a new job schedule model approach which takes into account the airport problem as a whole. This includes solving the integrated air traffic flow management problems at the airport. The department and the arrival managements are solved by job scheduling, but the taxi planning and the gate assignment are also studied with job schedule models. The paper integrates them in an it...

Memory mapped field programmable gate arrays (FPGAs) can be used to add expression level parallel processing to microprocessor-based systems. Multi-operand expressions can be computed in combinational logic eliminating microprocessor computation steps. FPGAs can capture operands as variables are assigned new values, eliminating separate load-stores to pass operands. Expressions can be for compu...

This paper presents a new approach to implement the Advanced Encryption Standard (AES), in the course, a Coarse-Grained Reconfigurable Processor, also called Reconfigurable CryptoProcessor is used to accomplish this assignment. The processor has been proved to be a candidate for cryptographic application. The prominent advantage of this processor is its high performance on cipher calculation ta...

Abstract: A reactive control strategy integrating time transfer delays is proposed to improve the water-asset management of networked hydrographical systems. The considered systems are characterized by large scale networks where each diffluence is equipped with a control gate and a measurement point. Modelling methods of the networked hydrographical systems with equipped diffluences are present...