Transistor designs based on using mixed Γ-L valleys for electron transport are proposed to overcome the DOS bottleneck while maintaining high injection velocities. Using a self consistent top-of-the-barrier transport model, improved current density over Si is demonstrated in GaAs/AlAsSb, GaSb/AlAsSb and Ge-on-insulator (Ge-OI) based single-gate (SG) thin-body n-channel metal-oxide-semiconductor...

Recent experiments have demonstrated that the performances of organic FETs strongly depend on the dielectric properties of the gate insulator. In particular, it has been shown that the temperature dependence of the mobility evolves from a metallic-like to an insulating behavior upon increasing the dielectric constant of the gate material. This phenomenon can be explained in terms of the formati...

We have investigated theoretically the effects of the charging energy to the normal metal–insulator–superconductor (NIS) tunnel junction used as a thermometer. We demonstrate by numerical calculations how the charging effects modify NIS thermometry, and how the voltage–to–temperature response and the responsivity |dV/dT | of a current biased thermometer are affected. In addition, we show that t...

Starting with a brief review on 0.1m (100 nm) CMOS status, this paper addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations. Among the issues discussed are: lithography, power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number f...

In this paper, the threshold voltage of fully depleted silicon on insulator device with geometry scale down below 100nm is investigated deeply. All the device simulations are performed using SILVACO Atlas device simulator. Several ways to control the threshold voltage are proposed and simulated. Threshold voltage changing with the silicon film thickness, channel doping concentration, gate oxide...

Solution-based organic field-effect transistors (OFETs) with low parasitic capacitance have been fabricated using a self-aligned method. The self-aligned processes using a cross-linking polymer gate insulator allow fabricating electrically stable polymer OFETs with small overlap area between the source-drain electrodes and the gate electrode, whose frequency characteristics have been investigat...

We demonstrate an integrated module of self-powered ferroelectric transistor memory based on the combination of a ferroelectric FET and a triboelectric nanogenerator (TENG). The novel TENG was made of a self-assembled polystyrene nanosphere array and a poly(vinylidene fluoride) porous film. Owing to this unique structure, it exhibits an outstanding performance with an output voltage as high as ...