This paper details Implementation of the Encryption algorithm AES under VHDL language In FPGA by using different architecture of mixcolumn. We then review this research investigates the AES algorithm in FPGA and the Very High Speed Integrated Circuit Hardware Description language (VHDL). Altera Quartus II software is used for simulation and optimization of the synthesizable VHDL code. The set o...

| This paper proposes a high-level synthesis system for datapath design of digital signal processing hardwares. The system consists of four phases: (1) DFG (dataow graph) generation, (2) scheduling, (3) resource binding, and (4) HDL (hardware description language) generation. In (1), the system does not generate only one best DFG representing a given behavioral description of a hardware, but mo...

Virtually every system designed today is an amalgam of hardware and software. Unfortunately, software and circuits that communicate across the hardware/software boundary are tedious and error-prone to create. This suggests a more automatic way to synthesize them. This paper presents the SHIM language, which combines imperative C-like semantics for software and RTL-like semantics for hardware to...

Since the advent of model checking it is becoming more common for languages to be given a semantics in terms of transition systems. Such semantics allow to model check properties of programs but are usually difficult to formally reason about, and thus do not provide a sufficiently abstract description of the semantics of a language. We present a set of transition system combinators that allow a...

This paper presents TPDL* (extended temporal profile description language), a general-purpose language to observe and condition dynamic systems by means of temporal and logical expressions. It describes how time is modelled in TPDL*, gives an overview of the language through its basic types, primitives and conditional constructs, and its use in computer-aided design of digital systems. The pape...

The paper describes the design process of discrete network – digital low-pass filter with Infinite Impulse Response (IIR filter). Based on given parameters that network should meet, and with the use of HDL hardware description language and MATLAB software package, hardware implementation of the filter transfer function was designed. Simulations confirmed the validity of the implementation desig...

This paper presents a logic based approach to hardware abstraction and composition based on the logic programming language Prolog. This is an attempt to satisfy the dual requirement of abstract hardware design and hardware efficiency. Central to this approach is a hardware description environment called HIDE, which provides more abstract and elegant hardware descriptions and compositions than a...

Hardware design using the hardware description language VHDL has to consider three independent property scales that in uence the design process from an abstract level to the gate level, namely the design view, the timing aspect, and the value representation. Considering this classi cation, a systematic way for design steps and their veri cation with special emphasis on VHDL is presented in this...

We introduce the use of asynchronous logic automata (ALA) for cryptography. ALA aligns the descriptions of hardware and software for portability, programmability, and scalability. An implementation of the A5/1 stream cipher is provided as a design example in a concise hardware description language, Snap, and we discuss a powerand timingbalanced cell design.