We present here a technique for allocation and binding for data path synthesis (DPS) using a Genetic Algorithm (GA) approach. This GA uses an unconventional crossover mechanism relying on a force directed data path binding completion algorithm. The data path is synthesized using some supplied design parameters. A bus-based interconnection scheme, use of multi-port memories, and provision for mu...

This paper presents the Flexible Architecture Representation , which is capable of representing complex hierarchical designs for synthesis as well as complex library components for hardware reuse. Contrary to previous representations used in high-level synthesis, the Flexible Architecture Representation supports multiple levels of controllers and thus enables a much larger degree of parallellis...

still not enough to satisfy all the LTCs and therefore serialized operations are folded if the total execution delay of the operations controlled by the places is smaller than the lower bound for the clock period. The only two places that can be folded together, given these criteria, are P 5 and P 6. Folding these two places decreases the length of all the LTCs and gives the control part in Fig...

|In integer linear programming (ILP), formulating a \good" model is of crucial importance to solving that model [1]. In this paper, we begin with a mathematical analysis of the structure of the assignment, timing, and resource constraints in high-level synthesis, and then evaluate the structure of the scheduling polytope described by these constraints. We then show how the structure of the cons...

This extended abstract presents ThreadPoolComposer, a high-level synthesis-based development framework and metatoolchain that provides a uniform programming interface for FPGAs portable across multiple platforms.

In this paper, the problem of reducing switching activity in on-chip buses at the stage of high-level synthesis is considered, and a high-level low power bus binding based on dynamic bit reordering is proposed. Whereas conventional methods use a fixed bit ordering between variables within a bus, the proposed method switches a bit ordering dynamically to obtain a switching activity reduction. As...

In this paper, we present a new methodology towards performing high-level synthesis. During high-level synthesis an algorithmic description is mapped to a structure of hardware components. In our approach, high-level synthesis is performed via program transformations. All transformations are performed within a higher order logic theorem prover thus guaranteeing correctness. Our approach is not ...

In this paper a flexible interface to high-level synthesis data (NEAT) is presented. NEAT offers three design views to common high-level synthesis data domains. Interand intra-domain relations are used to represent design relations between synthesis objects and to store synthesis results. To extend the functionality of the common synthesis interface programmers use object oriented programming t...

Dynamically reconfigurable co-processors (DRCs) are interesting design alternatives when both flexibility and performance are concerns. However, it is difficult to study the performance impact of including such devices into design when using traditional design methods and tools. In this paper, we present easily adaptable system-level techniques, which are able to perform fast exploration of dif...

This paper presents an approach to back-annotation of timing information in behavioral VHDL descriptions. In our approach, a behavioral VHDL description specifies the functionality and timing constraints of a design which is synthesized by a high-level synthesis tool. After synthesis the timing information of the design is back-annotated to the original VHDL description which is then used for s...