Energy consumption has become an important design consideration in modern processors. Therefore, microarchitects should consider energy consumption, together with performance, when designing the cache architecture, since it is a major power consumer in a processor. This paper proposes an accurate and energy-efficient way determination (instead of prediction) technique for reducing energy consum...

of the Dissertation Scalable Hardware Mechanisms for Superscalar Processors by Steven Daniel Wallace Doctor of Philosophy in Electrical and Computer Engineering University of California, Irvine, 1997 Professor Nader Bagherzadeh, Chair Superscalar processors fetch and execute multiple instructions per cycle. As more instructions can be executed per cycle, an accurate and high bandwidth instructi...

Emulating unimplemented instructions can reduce the cost and power requirements of a processor by allowing functional units to be removed. But the handling of unimplemented instruction exceptions in modern processors wastes fetch bandwidth and reduces throughput due to squashed instructions. Simultaneous Multithreaded (SMT) processors can avoid the waste by using multiple thread contexts to han...

Instruction caches are responsible for a high percentage of the chip energy consumption, becoming a critical issue for battery-powered embedded devices. We can potentially reduce the energy consumption of the first level instruction cache (L1-I) by decreasing its size and associativity. However, demanding applications may suffer a dramatic performance degradation, specially in superscalar multi...

The presence of precise exceptions in a processor leads to complications in its design. Some recent processor architectures have sacrificed this requirement for performance reasons at the cost of software complexity. We present an implementation strategy for precise exceptions in asynchronous processors that does not block the instruction fetch when exceptions do not occur; the cost of the exce...

Control dependences are one of the major limitations to increase the performance of current processors. A branch instruction supposes an interruption of the sequential flow of instructions traversing the pipeline because the next instruction address is unknown until the branch is executed. However, the fetch stage should introduce the successor instruction following the branch as soon as possib...

Abstract Architecture specifications such as Armv8-A and RISC-V are the ultimate foundation for software verification correctness criteria hardware verification. They should define allowed sequential relaxed-memory concurrency behaviour of programs, but hitherto there has been no integration full-scale instruction-set architecture (ISA) semantics with axiomatic models, either in mathematics or ...

Processors that can simultaneously execute multiple paths of execution will only exacerbate the fetch bandwidth problem already plaguing conventional processors. On a multiple-path processor, which speculatively executes less likely paths of hard-to-predict branches, the work done along a speculative path is normally discarded if that path is found to be incorrect. Instead, it can be beneficial...

Accurate branch prediction and instruction fetch prediction of a microprocessor are critical to achieve high performance. For a processor which fetches and executes multiple instructions per cycle, an accurate and high bandwidth instruction fetching mechanism becomes increasingly important to performance. Unfortunately, the relatively small basic block size exhibited in many general-purpose app...

The OpenSPARC T1 is a multithreading processor developed and open sourced by Sun Microsystems (now Oracle) [1]. We have added an implementation of our low-power Tagless-Hit Instruction Cache (TH-IC) [2] to the T1, after adapting it to the multithreading architecture found in that processor. The TH-IC eliminates the need for many instruction cache and ITLB accesses, by guaranteeing that accesses...