This paper addresses the problem of power dissipation during the buffer insertion phase of interconnect performance optimization. It is shown that the interconnect delay is actually very shallow with respect to both the repeater size and separation close to the minimum point. A methodology is developed to calculate the repeater size and interconnect length which minimizes the total interconnect...

This paper presents the measurement and characterization of multilayered interconnect capacitances for a 0.35m CMOS logic technology, which become a critical circuit limitation to high performance VLSI design. To measure multilayered capacitances of nonstacked, stacked, and orthogonally crossing interconnect lines, new test structures and measurement method are presented. The measured interconn...

As the capacities of eld-programmable gate arrays (FPGAs) grow, it becomes desirable to create FPGAs with embedded memory arrays. This paper examines the exibility of the interconnect structure that joins memory and logic. For architectures with only a few memory arrays, we nd that both the routability and the delay of circuits are insensitive to the memory/logic interconnect exibility, which i...

A characterization of the impact of interconnects at the system level is necessary to decide early in the design flow on ”how” and not just on “whether” all the devices can be connected. How the devices are connected depends on the interconnect architecture, which seems to be determined in a non transparent and sometimes ad hoc fashion by technologists. However, future DSM designs would benefit...

In current deep sub-micron chip design, interconnect effects start to dominate the chip’s performance. Therefore, the design flow has to become more interconnect-oriented. To limit the number of design iterations (and hence improve the time-to-market) one has to estimate interconnect parameters and their impact as early as possible. This is the goal of the field of System-Level Interconnect Pre...

ATM has been successfully used in Wide Area Networks (WAN) and Local Area Networks (LAN). A possible next step in this evolution is to use ATM for memory interconnect. This paper discusses how ATM can fulfill the functional and performance requirements in a memory interconnect, and the implications this will have for external ATM communication. We conclude that ATM can be used as a memory inter...

For future generation electronic circuits, a severe bottleneck is expected on the global interconnect level. With decreasing device dimensions, it is increasingly difficult to keep propagation delays acceptable and even with the most optimistic estimates for conductor resistivity and dielectric permittivity, the performance roadmap projected by the ITRS will not be met. Therefore there is a nee...

Interconnect has become a primary bottleneck in the integrated circuit design process. As CMOS technology is scaled, the design requirements of delay, power, bandwidth, and noise due to the on-chip interconnects have become increasingly stringent. New design challenges are continuously emerging, such as delay uncertainty induced by process and environmental variations. It has become increasingl...

We present the design of an ATM-based interconnect that serves as a high speed packet-switched equivalent of an I/O bus in a workstation/server. By effectively “extending” an external ATM network into the desk-area, the interconnect also functions as a high performance host-network interface. The prototype interconnect, which we are building as part of an ARPA sponsored gigabit local ATM testbe...

Reduction of interconnect delay and interconnect power has become a primary design challenge in recent CMOS technology generations. Spacing between wires can be modified so that line-to-line capacitances will be optimized for minimal power under timing constraints. In this paper, we present a novel algorithm for simultaneous multilayer interconnect spacing that minimizes the total dynamic power...