نتایج جستجو برای: low power adder circuit
تعداد نتایج: 1689202 فیلتر نتایج به سال:
Performance Analysis of a Low Power High Speed Hybrid Full Adder Circuit and Full Subtractor Circuit
Continuous scaling of the transistor size and reduction of the operating voltage has led to a significant performance improvement of integrated circuits. Low power consumption and smaller area are some of the most important criteria for the fabrication of DSP systems and high performance systems. In this paper there is try to determine the best solution to this problem by comparing a few adders...
Multiplication algorithms have considerable effect on processors performance. A new high-speed, low-power multiplication algorithm has been presented using modified Dadda tree structure. Three important modifications have been implemented in inner product generation step, inner product reduction step and final addition step. Optimized algorithms have to be used into basic computation components...
Power consumption has emerged as a primary design constraint for integrated circuits (ICs). In the Nano meter technology regime, leakage power has become a major component of total power. Full adder is the basic functional unit of an ALU. The power consumption of a processor is lowered by lowering the power consumption of an ALU, and the power consumption of an ALU can be lowered by lowering th...
A novel low power and low transistor count static energy recovery full adder (SERF) is presented in this paper. The power consumption and general characteristics of the SERF adder are then compared against three low power full adders; the transmission function adder (TFA), the dual value logic (DVL) adder and the fourteen transistor (14T) full adder. The proposed SERF adder design was proven to...
-This paper explains a new approach to design Exclusive-OR gate using 2 transistors. A full adder circuit has been designed by using proposed 2T Exclusive-OR circuit and a transmission gate is used extensively in very large-scale integration (VLSI) application. The power dissipation of the adder is in range of 421.7256uw to 581.542uw in 0.35 um technology with a voltage supply is in the range o...
Reversible circuit designing is the area where researchers are focussing more and more for the generation of low loss digital system designs. Researchers are using the concept of Reversible Logic in many areas such as Nanotechnology, low loss computing, optical computing, low power CMOS design etc. Here we have proposed a novel design approach for a 2-bit binary Arithmetic Logic Unit (ALU) usin...
To reduce power consumption in electronic designs, new techniques for circuit design must always be considered. Floating-gate MOS (FGMOS) is one of those techniques and has previously shown potentially better performance than standard static CMOS circuits for ultra-low power designs. One reason for this is because FGMOS only requires a few transistors per gate and still retain a large fan-in. A...
In this paper, the design of a low power and high performance dynamic circuit using a new CMOS domino logic family called feedthrough logic is presented. The need for faster circuits with low power dissipation has made it common practice to use feedthrough logic. The proposed circuit for low power improves dynamic power consumption as compared to the existing feedthrough logic and improves its ...
In this paper, the design of a low power and high performance dynamic circuit using a new CMOS domino logic family called feedthrough logic is presented. The need for faster circuits with low power dissipation has made it common practice to use feedthrough logic. The proposed circuit for low power improves dynamic power consumption as compared to the existing feedthrough logic and improves its ...
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