This paper presents an improved master–slave bipolar Si–SiGe HBT comparator design for ultra-high-speed data converter applications. The latch is maintained during the track stage facilitating quick transition back to the latch stage, increasing the sampling speed of the comparator. Implemented in a 0.5m 55-GHz BiCMOS Si–SiGe process, this comparator consumes approximately 80 mW with sampling s...

Comparator circuit model was originally introduced in [5] (and further studied in [2]) to capture problems which are not known to be P-complete but still not known to admit efficient parallel algorithms. The class CC is the complexity class of problems many-one logspace reducible to the Comparator Circuit Value Problem and we know that NLOG ⊆ CC ⊆ P. Cook et al [2] showed that CC is also the cl...

Suppose that there is a sorted sequence and at most k elements change their values, for some k n. We present a comparator network of depth 4 log n + O((log k log log n) 2) that makes the sequence sorted again.