In this paper, we discuss an optimization-based approach for design space exploration of analog circuits, i.e., how some design parameters affect the circuit performance and cost. By this exploration the designer is guided to make judicious trade-offs among the remaining design parameters. For the design space exploration, which is expensive in terms of computation time, we use an optimization-...

In a companion paper of this session [1] we formally defined the notion of equivalence classes of circuits which are physical clones of an existing benchmark seed circuit created by the GEN tool. Here we use well-known partitioning and placement tools to study the behaviour of clone circuits. We outline a simple methodology for using equivalence classes of clone circuits for benchmarking. We th...

The objective of this paper is to demonstrate the practice of the SubGraph Isomorphism (SGI) algorithm on solving the problem of SubCircuit Extraction (SCE). The netlist representation of circuits is discussed first because it has caused the dilemma to the existing SCE approach. Then, based on mapping focus of Edge Unit (EU), an algorithmic solution is exhibited to fulfill the void of circuit c...

We demonstrate the feasibility of using image analysis for automatically converting from a scanned electronic circuit schematic to a netlist of the components and their connections. A preprocessing stage removes non-components from the image (component label and values). The image is then segmented to produce a set of graphical primitives (lines, circles, and arrows). The recognition stage uses...

In this paper, we discuss an optimization-based approach for design space exploration of analog circuits, i.e., how some design parameters affect the circuit performance and cost. By this exploration the designer is guided to make judicious trade-offs among the design parameters. For the design space exploration, which is expensive in terms of computation time, we use an optimization-based appr...

-An increasing constraint in implementing algorithms in digital signal processors is low power design. In order to avoid time consuming and uneconomic redesigning it is essential to optimise the sources of power consumption in the earliest possible stage in the IC design cycle. This paper presents CapCount, a novel high-level dynamic power estimation tool, operating as an add-on tool to Synopsy...

Dual-rail encoding, return-to-spacer protocol and hazard-free logic can be used to resist power analysis attacks by making energy consumed per clock cycle independent of processed data. Standard dual-rail logic uses a protocol with a single spacer, e.g. all-zeroes, which gives rise to energy balancing problems. We address these problems by incorporating two spacers; the spacers alternate betwee...

While cloud computing is growing at a remarkable speed, privacy issues are far from being solved. One way to diminish privacy concerns is to store data on the cloud in encrypted form. However, encryption often hinders useful computation cloud services. A theoretical approach is to employ the so-called fully homomorphic encryption, yet the overhead is so high that it is not considered a viable s...

This paper presents the applicability of a cosimulation methodology based on an object-oriented simulation environment, to multi-domain and multi-language systems design. This methodology start with a system model given as a netlist of heterogeneous components and enables the systematic generation of simulation models for multi-domain and multi-language heterogeneous systems. For experiments, w...