Since Network-on-Chip (NoC) uses network interfaces (NIs) to improve the design productivity, by now, there have been a few papers addressing the design and implementation of a NI module. However, none of them considered the difference of address encoding methods between NoC and the traditional bus-shared architecture. On the basis of this difference, in the paper, we introduce a transmit mecha...

This paper presents the evaluation of a Network-onChip (NoC) that offers load balancing for Systems-on-Chip (SoCs) dedicated for multimedia applications that require high traffic of variable bitrate communication. The NoC is based on a technique that allows the interleaving of flits from different flows in the same communication channel, and keep the load balancing without a centralized control...

The NoC consists of processing element (PE), network interface (NI) and router. This paper proposes a hybrid scheme for Netwok of Chip (NoC), which aims at obtaining low latency and low power consumption by concerning wired and wireless links between routers. The main objective of this paper is to reduce the latency and power consumption of the network on chip architecture using wireless link b...

Network-on-Chip (NoC) has recently emerged as an efficient communication solution for the System-on-Chip (SoC) design. Design space exploration and performance evaluation are the most essential task in NoC design. In this paper, an ABC based design space exploration framework for the NoC design is proposed. The objective of the design space exploration is to minimize the total energy consumptio...

Dual core microprocessors are currently available and higher processor-count architectures will dominate the multicore market. A complex part of these higher order multicore designs will be the interconnection scheme that exists onchip and how exactly that interconnection is best used and configured. While FPGAs currently support a variety of onchip bus interconnects, there is a gap in the tool...

Increasing heterogeneous software and hardware blocks constitute complex ICs known as System on Chip (SoC). These blocks are conceived as intellectual property (IP) cores. Designers are developing SoCs by using IP cores reuse, which include interconnection architecture and interface to peripheral devices.Because of the SoC growing complexity, some researchers tend to concentrate more on the com...

Chip Multi-Processor (CMP) architectures have become mainstream for designing processors. With a large number of cores, Network-On-Chip (NOC) provides a scalable communication method for CMP architectures, where wires become abundant resources available inside the chip. NOC must be carefully designed to meet constraints of power and area, and provide ultra low latencies. In this paper, we propo...

The Network-on-Chip (NoC) is an enabling technology to integrate large numbers of embedded cores on a single die. Traditional multi-core designs based on the NoC paradigm suffer from high latency and power dissipation due to the inherent multi-hop nature of communication. The performance of NoC fabrics can be significantly enhanced by introducing long-range, low power, and high-bandwidth single...

Evaluation of trade-offs between dynamical characteristics and architecture design on large-scale networks is demanded for engineering solutions. We study dynamical characteristics of complex networks through both packet traffic simulation and theoretical network analysis to explore highperformance NoC (network-on-chip) architectures. To achieve efficient communication with hundreds of function...

nowadays network-on-chips is used instead of system-on-chips for better performance. this paper presents a new algorithm to find a shorter path, and shows that genetic algorithm is a potential technique for solving routing problem for mesh topology in on-chip-network.