Testing two-port memories requires the use of single-port tests as well as special two-port tests; the test strategy determines which tests have to be used. Many two-port memories have ports which are read-only or write-only; this impacts the possible tests for single-port and two-port memories, as well as the test strategy. This paper discusses the consequences of the port restrictions (read-o...

A read-only transaction (ROT) does not modify any data. The main issues regarding processing ROTs are correctness, data currency and performance. Two-phase Locking (2PL) protocol is widely used for concurrency control with serializabilty as correctness criteria. Even though 2PL processes ROTs correctly with no data currency related issues, the performance deteriorates as data contention increas...

Nowadays, concurrency control for XML data is a big research problem. There are a number of researchers working on this problem, but most of the proposed methods are based on the two-phase locking protocol, which potentially leads to a high blocking rates in data-intensive XML-applications. In this paper we present and evaluate SXDGL, a new snapshot based concurrency control protocol for XML da...

In this paper, we investigate the approach of using separate algorithms to process read-only transactions in realtime systems. A read-only transaction (ROT) is a transaction that only reads, but does not update any data item. Since there is a significant proportion of ROTs in several real-time systems, it is important to investigate how to process ROTs effectively. Using an algorithm to process...

A read-only transaction (ROT) does not modify any data. Efforts are being made in the literature to improve the performance of ROTs without correctness and data currency issues. The widely used twophase locking protocol (2PL) processes the transactions without any correctness and data currency issues. However, the performance of 2PL deteriorates with data contention. Snapshot isolation (SI)-bas...

One of the important issues in embedded system design is to optimize program code for the microprocessor to be stored in ROM. In this paper, we propose an integrated approach to the DSP address-code generation problem for minimizing the number of addressing instructions. Unlike previous works, in which code scheduling and offset assignment are performed sequentially without any interaction betw...