In his outstanding work on Communicating Sequential Processes, Hoare has defined two fundamental binary operations allowing to compose the input processes into another, typically more complex, process: sequential composition and concurrent composition. Particularly, the output of the latter operation is a process in which any event not shared by both operands can occur whenever the operand that...

Reconfigurable computers (RCs) are gaining rising attention as an alternative to traditional processors for many applications. However, using RCs for operations with either large-size operands or large number of operands can be challenging given the bounded reconfigurable resources. In this paper, we propose a systematic methodology based on a Divide-and-Conquer technique for the implementation...

In this work we propose a new method for designing modulo 2+1 multipliers for diminished-1 operands. Our multipliers compared to the already known tree architecture offer enhanced operation speed for the majority of n values, with similar area complexities. They also have very regular structure, and can be pipelined at the full-adder level.

Fault tolerance requires the inclusion of redundant information. In this paper an on-line error detecting adder is presented in which the redundant information serves a dual purpose. It provides fault tolerance during the arithmetic operations while also providing a method by which addition is constrained to become a constant delay operation regardless of the word size of the operands.

verbally, methodologically, formalistically and graphically. On the web site several articles and books in English, German and Slovenian (Meditations) are published free of charge. At the beginning, there are Basic axioms for formula composition as syntactically as partially semantic set of the very basic rules, defining the so-called informational-conscious externalism, internalism, metaphysic...

Current microprocessors are designed to execute instructions in parallel and out of order. In general, superscalar processors fetch instructions in order. After the branch prediction logic determines whether a branch is taken (or not) and its target address, the processor decodes the instructions and renames the register operands, removing name dependences introduced by the compiler. Because pr...

In this paper we present a Concurrent Error Detection (CED) technique that can be applied to behavioral RTL models of data dominated systems. The technique obtains CED through duplication of operations with shifted operands. Duplication is performed according to transformation rules that can automatically be applied to a behavioral model. Preliminary experimental results show the viability of t...

This paper presents two new radix-8 division algorithms. These algorithms are based on comparisons of relatively narrow operands, rather than on confusing P-D plots. It is hoped that by implementing comparison-based division algorithms, Pentium-style bugs would become less likely.

We present data structures and an eecient algorithm realizing eecient performance driven generation of integer adders. The generator is parameterized in n, the operands' bitlength, and tn, the delay of the addition. It outputs an area minimal n-bit adder of the conditional-sum type with delay tn, if such a circuit exists.

Current microprocessors are designed to execute instructions in parallel and out of order. In general, superscalar processors fetch instructions in order. After the branch prediction logic determines whether a branch is taken (or not) and its target address, the processor decodes the instructions and renames the register operands, removing name dependences introduced by the compiler. Because pr...