Existing wireless communication interface has free space signal radiation which drastically reduces the received signal strength and hence reduces the throughput efficiency of Hybrid Wired-Wireless Network-on-Chip (WiNoC). This paper addresses the issue of throughput degradation by replacing the wireless layer of WiNoCs with a novel Complementary Metal Oxide Semiconductor (CMOS) based waveguide...

The rapid development of Network-on-Chip (NoC) calls for a systematic approach to evaluate and fairly compare various NoC architectures. In this specification, we define a generic NoC architecture, a comprehensive set of synthetic workloads as micro-benchmarks, workload scenarios and evaluation criteria. These micro-benchmarks enable to measure and pinpoint particular properties of NoC architec...

The voltage/frequency island (VFI) design paradigm is a practical architecture for energy-efficient networks-on-chip (NoC) systems. In VFI-based NoC systems, each island can be operated with different voltage and clock frequency and thus it is important to carefully partition processing elements (PEs) into islands based on their workloads and communications. In this paper, we propose an energy-...

Nowadays, the growing demand for supporting multiple applications causes to use multiple IPs onto the chip. In fact, finding truly scalable communication architecture will be a critical concern. To this end, the Networks-on-Chip (NoC) paradigm has emerged as a promising solution to on-chip communication challenges within the silicon-based electronics. Many of today’s NoC architectures are based...

C-based cycle-accurate simulations are used to evaluate the performance of a Network-On-Chip (NoC) based on an improved version of the modified Fat Tree topology. The modification simplifies routing further and guarantee orderly reception of packets without any loss of performance. Several traffic models have been used in these simulations; Bursty and non-bursty traffic with uniformlydistribute...

The performance of network-on-chip (NOC) largely depends on the underlying routing techniques. A routing technique has two constituencies: output selection and input selection. This paper focuses on the improvement of input selection part. Two traditional input selections have been used in NOC, firstcome-first-served (FCFS) input selection and Round-Robin input selection. Also, recently a conte...

General purpose routing algorithms for a network-on-chip (NoC) platform may not be able to provide sufficient performance for some communication intensive applications. This may be because of low adaptivity offered by a general purpose routing algorithm resulting in some links getting highly congested. In this study the authors demonstrate that it is possible to design highly efficient applicat...

Three-Dimensional Networks-on-Chip (3D-NoC) has been presented as an auspicious solution merging the high parallelism of Network-on-Chip (NoC) interconnect paradigm with the high-performance and lower interconnect-power of 3-dimensional integration circuits. However, 3D-NoC systems are exposed to a variety of manufacturing and design factors making them vulnerable to different faults that cause...

Recently, optical interconnect has emerged as a possible alternative to electrical interconnect at chip-to-chip and on-chip length scales because of its potential to overcome power, delay, and bandwidth limitations of traditional electrical interconnect. This thesis examines the issues of variation involved in the implementation of a robust on-chip optical signal distribution network. First, th...