A phase-locked loop (PLL) with frequency resolution in steps smaller than the reference oscillator is often wanted. Although this can be accomplished with a fractional-N PLL, in which the divide ratio is varied between N and N+1 at a defined rate, this technique generates undesired spurs. An alternative is to use a delta-sigma modulator in which the divide ratio (divisor) is dithered, eliminati...

In this paper, an integral-type half-tangent phase-locked loop (IHTan-PLL) is proposed for the varying-frequency AC grids of more electric aircraft (MEA). First, performance synchronous reference frame (SRF-PLL) and (HTan-PLL) discussed from a large-signal viewpoint. When frequency changes largely, SRF-PLL has many oscillations endures rather long transient process. The HTan-PLL can address lar...

This paper deals with different approaches to design Phase Locked Loop (PLL) frequency synthesizer. PLL system responds to both frequency and phase of the input signals, automatically raising or lowering the frequency of controlled oscillator until it is matched to the reference in both frequency and phase. The performance of PLL frequency synthesizer is improved by using different Voltage cont...

(VCO) phase-locked loop (PLL) and ring-VCO PLL topologies with low-phase noise. Differential control loops are used for the PLL locking through a symmetrical transformer-resonator or bilaterally controlled varactor pair. A differential compensation mechanism suppresses out-band spurious tones. The prototypes of the proposed PLL are implemented in a CMOS 65-nm or 45-nm process. The measured resu...

An ASIC design of Dual Edge Triggered Phase Detector(DET PD) for Delay locked loop(DLL) and Phase locked loop(PLL) applications is proposed in this paper.The proposed DET PD has high locking speed and less jitter. The designs are based on TSPC flip flop logic, which overcomes the issue of narrow capture range. The Double edge triggered phase detector dissipates less power than conventional desi...

In this paper, a review of Phase Locked Loop (PLL) algorithms and symmetrical component extraction methods intended for grid-connected power electronic converters are presented. Proposed classification is based on voltage representation in three coordinates: natural (abc), stationary (αβ) and rotating coordinates (dq). The three selected algorithms are described in details: Dual Second Order Ge...

In this paper, a new strategy of switchable CMOS phase-locked loop frequency synthesizer is proposed to increase its tuning range. The switchable PLL which integrates two phase-locked loops with different tuning frequencies are designed and fabricated in 0.5 μm n-well CMOS process. Cadence/Spectre simulations show that the frequency range of the switchable phased-locked loop is between 320 MHz ...

We present an analytical frequency-domain phase noise model for fractional-N phase-locked loops (PLL). The model includes the noise of the crystal reference, the reference input buffer, the voltage-controlled oscillator (VCO), the loop filter, charge pump device noise, sigma-delta modulator (SDM) noise including its effect on the in-band phase noise. Thermal device noise of the charge pump and ...

Phase locked loop and synchronization techniques are one of the most important issues for operating grid-interfaced converters in practical applications, which involve Distributed Power Generation Systems, Flexible AC Transmission Systems (FACTS), and High Voltage Direct Current (HVDC) Transmission, and so on. This paper presents a comprehensive review of the recently developed phase locked loo...

-A PLL is a closed loop system that locks the phase of an output signal to an input reference signal. The term “lock” refers to a constant or zero phase difference between two signals. The components of PLL are the Phase Frequency Detector (PFD), the charge pump (CP), the low pass filter (LPF), and the voltage controlled oscillator (VCO). In which the charge pump has been modified in order to o...