Instruction predication is an attractive method for improving the throughput of a pipelined processor by eliminating the adverse side-effects of branch operations. Although it may alone help to prevent simple power analysis (SPA) type attacks by masking branch execution, predication systems can also be augmented to allow a building block for defence against more powerful cryptographic attacks. ...

Cordic based cascade orthogonal IIR digital lters possess desirable properties for VLSI implementations such as local connection, regularity, absence of limit cycle and overrow oscillations, and good nite word-length behavior. However, the achievable sample rate of these lters is limited, since these structures can't be pipelined at ner levels (such as bit or multi-bit level) due to the presenc...

This article presents a latency-optimized implementation of the SIMECK lightweight block cipher on field-programmable-gate-array (FPGA) platform with and key lengths 32 64 bits. The critical features our architecture include parallelism, pipelining, dedicated controller. Parallelism splits digits data blocks into smaller segments. Then, we use each segmented in parallel for encryption decryptio...

The paper proposes a new hierarchical hypernet which is an extension of hypernet suggested by Hwang and Ghosh. The hypernet is generalised for any value ofG = 2* for 0 < x <</— 2 where d is the dimension of the basic hyper cube. The mathematical formulas for the network parameters are developed as a function ofG. The hier (d,h,G) hypernet consists of(d,l,G), (d,2,G), (d,3,G), (d,h — l,G), (d,h,...