In the new Internet of Things (IoT) era, embedded Field-Programmable Gate Array (FPGA) technology is enabling deployment custom-tailored IoT solutions for handling different application requirements and workloads. Combined with open RISC-V Instruction Set Architecture (ISA), FPGA provides endless opportunities to create reconfigurable devices accelerators coprocessors tightly loosely coupled pr...

It has been a common myth that x86-64 processors suffer in terms of energy efficiency because of their complex instruction set. In this paper, we aim to investigate whether this myth holds true, and determine the power consumption of the instruction decoders of an x86-64 processor. To that end, we design a set of microbenchmarks that specifically trigger the instruction decoders by exceeding th...

Power consumption is an increasingly important consideration in the design of mixed hardware/software systems. This work defines the notion of instruction subsetting and explores its use as a means of reducing power consumption from the system level of design. Instruction subsetting is defined as creating an application specific instruction set processor from a more general processor, such as a...

The general purpose processors that are used in embedded systems must support constraints like execution time, power consumption, code size and so on. On the other hand an Application Specific Instruction-set Processor (ASIP) has advantages in terms of power consumption, performance and flexibility. In this paper, a 16-bit Application Specific Instruction-set processor for the sensor data trans...

We use the Xilinx Virtex II ProTM technology as prototyping platform to design a MOLEN polymorphic processor, a custom computing machine based on the co-processor architectural paradigm. The PowerPC embedded in the FPGA is operating as a general purpose (core) processor and the reconfigurable fabric is used as a reconfigurable co-processor. The paper focuses on hardware synthesis results and ex...

Microprocessor is a general purpose IC which follows the instructions given to it, and the instructions set for the microprocessor designed such a way that it can handle any type of computations [4] . Different type of architectures are available in the market like CISC, RISC, ARM SHARC etc. all of them have their own different approaches to perform computations. This Paper work which is RISC c...

This paper covers the design technique of an enhanced Reduce Instruction Set Computer (RISC)-based processor core using application-specific instruction-set processor (ASIP) methodology. The processor core, called UTeMRISC03, is essentially a synthesizable processor written in Verilog HDL with a 16-bit data path and a 22-bit wide instruction. Using ASIP methodology, the processor architecture i...

In a sensor network, exploiting the correlation among different sources allows a significant reduction of the transmitted energy at the cost of a complex decoder scheme. This paper introduces the first hardware implementation for joint source-channel decoding of correlated sources. Specifically, a dual-clustered VLIW processor with a highly optimized datapath is presented.

EPIC processor is one of the best ways to exploit the instruction level parallelism where multiple instructions are issued explicitly by the compiler. VLIW processor is the evolution of EPIC processing paradigm. Very Long Instruction Word (VLIW) is multi-issue processors that try to extract parallelism statically by the compiler .It execute a long instruction that consist of multiple operation....

In this paper we consider a set of multimedia applications and investigate the potential performance impact a reconfigurable microcoded processor can provide when added to a general purpose core processor. In a design space exploration, considering MPEG2 and JPEG benchmarks, we investigate performance boundaries, memory bottlenecks and the influence the core and reconfigurable processor communi...