Antenna arrays are of perennial interest and relevance to RF wireless system designers, indeed the rise of 5G is showing their importance is only growing. Most implementations of linear arrays use phase shifters to feed the array and hence form the main-lobe beam. In the 1960s, a technique using RF switches and Fourier analysis was discovered to be a viable alternative to phase shifters called ...

The design of A 2.4-GHz CMOS Class E cascode power amplifier (PA) for GSM applications in TSMC 0.18-μm CMOS technology present in this paper. Proposed Class E cascode PA topology is a single-stage topology in order to minimize the device stress problem. A parallel capacitor is connected across the transistors for efficiency enrichment also for dominating the effect of parasitic capacitances at ...

This work proposed a low power and high gain folded cascode CMOS operational amplifier with a common mode feedback (CMFB) for Pipeline ADC. The proposed design is implemented in 0.13-μm Silterra CMOS technology. The folded cascode topology has been used for obtaining a high gain and low power consumption. Meanwhile, the CMFB is modified circuit to be a double detection to stabilize the output o...

A gain boosting method without noise-figure degradation by optimizing interstage matching in a cascode low-noise amplifier (LNA) with emitter-degeneration inductor is demonstrated at 5.2 GHz using 2m GaInP/GaAs HBT technology. A low-pass LC matching network is inserted in the interstage of a conventional cascode LNA with emitter-degeneration-inductor to enhance the gain with the same current co...

Low Noise Amplifier and Mixer design considerations for 2.45 GHz Bluetooth applications have been studied. A detailed noise analysis is presented. A design strategy for an inductively degenerated common-source LNA with cascode transistor and current-commutating Mixer is proposed, considering the tradeoffs between noise, linearity, power consumption and matching of impedances. Additionally, this...

A novel circuit topology for high-gain distributed amplifiers is presented in this study. Based on the conventional distributed architecture, the gain cells are realized by cascading cascode stages for gain enhancement. In addition, the stagger-tuning technique is extensively utilized in the design of the cascode stages as well as the cascaded stages, leading to significant improvement in terms...

Cascode CMOS op-amps use a large number of external bias voltages. This results in numerous drawbacks, namely, an area and power overhead, susceptiblity of the bias lines to noise and cross-talk and high sensitivity of the bias point to process variations. In this paper we present a self-biasing technique for folded cascode CMOS op-amps that uses no additional devices and no baas voltages other...

This paper addresses the issues involved in designing 1V Op-amp in standard digital CMOS technology. Bulk-driving technique is used to circumvent the metal–oxide semiconductor field-effect transistor turn-on (threshold) voltage requirement. The Op-amp will be designed in a Europractice 0.7μm n-well CMOS process having threshold voltage of 0.76V and –1V for NMOS and PMOS respectively. Simple and...