A gain boosting method without noise-figure degradation by optimizing interstage matching in a cascode low-noise amplifier (LNA) with emitter-degeneration inductor is demonstrated at 5.2 GHz using 2m GaInP/GaAs HBT technology. A low-pass LC matching network is inserted in the interstage of a conventional cascode LNA with emitter-degeneration-inductor to enhance the gain with the same current co...

Low Noise Amplifier and Mixer design considerations for 2.45 GHz Bluetooth applications have been studied. A detailed noise analysis is presented. A design strategy for an inductively degenerated common-source LNA with cascode transistor and current-commutating Mixer is proposed, considering the tradeoffs between noise, linearity, power consumption and matching of impedances. Additionally, this...

A novel circuit topology for high-gain distributed amplifiers is presented in this study. Based on the conventional distributed architecture, the gain cells are realized by cascading cascode stages for gain enhancement. In addition, the stagger-tuning technique is extensively utilized in the design of the cascode stages as well as the cascaded stages, leading to significant improvement in terms...

This paper addresses the issues involved in designing 1V Op-amp in standard digital CMOS technology. Bulk-driving technique is used to circumvent the metal–oxide semiconductor field-effect transistor turn-on (threshold) voltage requirement. The Op-amp will be designed in a Europractice 0.7μm n-well CMOS process having threshold voltage of 0.76V and –1V for NMOS and PMOS respectively. Simple and...

A novel low-power kick-back reduced comparator for use in high-speed flash analog-to-digital converters (ADC) is presented. The proposed comparator combines cascode transistors to reduce the kick-back noise with a built-in threshold voltage to remove the static power consumption of a reference. Without degrading other figures, the kick-back noise is reduced by a factor 8, compared to a previous...

Now a day’s technology enhancement is at a blistering pace. Merely VLSI has a meteoric rise due to the adoption of new techniques. Static CMOS had a limitation of deploying constant power supply. Less power dissipation is an essential attribute for any optimized design. Varying the power supply is the very thing for preventing the power dissipation. An adiabatic logic is a new technique to redu...

A fully integrated CMOS wideband Low Noise Amplifier (LNA) operating over 2.3–7 GHz is designed and fabricated using a 0.18 μm CMOS process. The proposed structure is a common sourcecommon source (CS-CS) cascode amplifier with a coupling capacitor. It realizes both low voltage drop at load resistor (Rload) and high gain over 2.3–7 GHz with simultaneous noise and input matching and low power con...

Abstract—This work presents a fully differential CMOS amplifier consisting of two self-biased gain boosted inverter stages, that provides an alternative to the power hungry operational amplifier. The selfbiasing avoids the use of external biasing circuitry, thus reduces the die area, design efforts, and power consumption. In the present work, regulated cascode technique has been employed for ga...

A novel low voltage self-biased high swing cascode current mirror (SHCCM) employing bulk-driven NMOS transistors is proposed in this paper. The comparison with the conventional circuit reveals that the proposed bulk-driven circuit operates at lower voltages and provides enhanced bandwidth with improved output resistance. The proposed circuit is further modified by replacing the passive resistan...