The aim with this paper is to design a high efficient sequential ATPG on single stack-at fault model. A new approach for sequential circuit test generation is proposed in this paper. With combining the advantage of logic simulation based ATPG and fault simulation based ATPG, higher fault coverage and shorter test sequential length are achieved for benchmark circuit instead of pure logic or faul...

In this paper, we propose a modeling approach that captures the dependence of the power dissipation of a (combinational or sequential) logic circuit on its input/output signal switching statistics. The resulting power macromodel, consists of a quadratic or cubic equation in four variables, that can be used to estimate the power consumed in the circuit for any given input/output signal statistic...

This paper examines the problem of minimizing the area of a synchronous sequential circuit for a given clock period speci cation under the standard-cell paradigm. This is e ected by appropriately selecting a size for each gate in the circuit from a standard-cell library, and by adjusting the delays between the central clock distribution node and individual ipops. Traditional methods treat these...

Design and synthesis of basic functional circuits are the fundamental tasks of synthetic biologists. Before it is possible to engineer higher-order genetic networks that can perform complex functions, a toolkit of basic devices must be developed. Among those devices, sequential logic circuits are expected to be the foundation of the genetic information-processing systems. In this study, we repo...

Multi-threshold voltage CMOS (MTCMOS) is the most widely used circuit technique for suppressing the subthreshold leakage currents in idle circuits. When a conventional sequential MTCMOS circuit transitions from the sleep mode to the active mode, signi ̄cant bouncing noise is produced on the power and ground distribution networks. The reliability of the surrounding active circuitry is seriously d...

We propose an exact clustering with retiming algorithm to minimize the clock period for sequential circuits. Without moving ip-ops (FF's) by retiming, conventional clustering algorithms can only handle combina-tional parts and therefore cannot achieve the best cycle time. Pan et al. 2] have proposed an optimal algorithm under the unit gate delay model. We propose a more powerful and faster algo...

This paper overviews clock design problems related to the circuit reliability in deep submicron design technology. The topics include the clock polarity assignment problem for reducing peak power/ground noise, clock mesh network design problem for tolerating clock delay variation, electromagnetic interference aware clock optimization problem, adjustable delay buffer allocation and assignment pr...

In this paper, the design of pre-settable adiabatic flip-flops and sequential circuits based on the newly proposed Energy efficient adiabatic Logic (EEAL) is presented. EEAL is based on differential cascode voltage swing (DCVS) logic, uses only a single sinusoidal source as supply-clock. This not only ensures lower energy dissipation, but also simplifies the clock design which would be otherwis...

This paper states the necessary and sufficient conditions for the existence of a feedforward inverse for a feedforward linear sequential circuit and gives an implicit procedure for constructing such inverses. It then goes on to give the necessary and sufficient conditions for the existence of general inverses with finite delay and gives procedures for constructing a class of such inverses. The ...

We propose a formulation of the sensitization constraints that must be satisfied by all true paths in a sequential circuit and suggest a number of approximations to these constraints aimed at simplifying their computation while capturing their essential dependencies. Using one of these approximations we show how an existing combinational timing analysis tool, can be easily augmented to identify...