Silicon on insulator (SOI) CMOS offers performance gain over bulk CMOS mainly due to reduced parasitic capacitances and latchup. It is most promising technology when low cost low power and low voltage suppply is required. kink effect and self heating are two important points of concern in case of SOI MOSFET. In this paper we first briefly discuss the SOI technology, kink effect and lattice heat...

This work presents a monolithic laterally-coupled wide-spectrum (350 nm < λ < 1270 nm) optical link in a silicon-on-insulator CMOS technology. The link consists of a silicon (Si) light-emitting diode (LED) as the optical source and a Si photodiode (PD) as the detector; both realized by vertical abrupt n+p junctions, separated by a shallow trench isolation composed of silicon dioxide....

Applications involving smart cards have rapidly emerged since a few years. Up to now, chips are realized in conventional bulk technology. But as the need for performance rises, alternative technologies must be investigated. In this paper we study the feasibility of realizing the blocks for a smart card chip in Silicon-On-Insulator (SOI) technology. For most of the circuit blocks, SOI realizatio...

The feasibility of fabricating wireless optical components on Silicon-on-Insulator (SOI) is investigated. Using arrays of grating couplers, a so-called phased array is constructed allowing beam steering and sending light to and receiving light from free space. Using a phased array at the receiver side also allows for more complex modulation formats since light is now captured coherently before ...

This paper describes 0.18um CMOS silicon-on-insulator (SOI) technology and design techniques for SOI RF switch designs for wireless applications. The measured results of SP4T (single pole four throw) and SP8T (single pole eight throw) switch reference designs are presented. It has been demonstrated that SOI RF switch performance, in terms of power handling, linearity, insertion loss and isolati...

CMOS implementations for RF applications often employ technology modifications to reduce the silicon substrate loss at high frequencies. The most common techniques include the use of a high-resistivity substrate (ρ>10Ω-cm) or silicon-on-insulator (SOI) substrate and precise bondwire inductors [1, 2]. However, these techniques are incompatible with low-cost CMOS manufacture. This design demonstr...

A metallic coupler is proposed to interface a silicon on insulator (SOI) waveguide with a narrow hybrid plasmonic waveguide (200× 200 nm). The device operation is investigated and optimized to attain the best tradeoff between the mode confinement and the propagation loss. Calculations reveal that a high confinement and low loss of the energy is achieved from a silicon slab waveguide into the di...

Smart power ICs, which monolithically integrate low-loss power devices and control circuitry, have attracted much attention in a wide variety of applications [1], [2]. Commonly used smart power devices are the LDMOS and LIGBT implemented in bulk silicon or SOI (Silicon on Insulator). One of the key issues in the realization of such ‘smart power’ technology is the isolation of power devices and ...