نتایج جستجو برای: static random access memory
تعداد نتایج: 919182 فیلتر نتایج به سال:
Leakage control during circuit operation is more challenging than standby mode control due to the short time to deactivate blocks, large overhead energy and run-time leakage variations. This paper proposes circuit techniques that address these challenges to reduce run-time leakage in on-die SRAM caches. A source-biased gated-ground SRAM is proposed; an efficient way to utilize this technique un...
To reduce the dynamic power consumption in SRAM a new design technique is proposed here. The proposed technique is compared with 8T SRAM cell design technique using 0.18 micron technology. Simulation results indicates that the proposed technique provides an improvement of 64% in bitline leakage ,22.64% in write ‘0’ power, 30.68% in write ‘1’ power over 8T SRAM cell design technique.
Six layout variations of the 6T SRAM cell are examined and compared. The comparison includes four conventional cells, plus the thin cell commonly used in industry and a recently proposed ultra-thin cell. The layouts of the cells are presented and corresponding memory arrays are implemented at 65, 45 and 32 nm using 3-metal CMOS n-well process. The obtained designs are compared in terms of area,...
March tests have been widely used for detecting functional faults during SRAM testing. Recent development has extended the March test for diagnostic purpose to locate and identify the fault types. This paper analyses March algorithms for detection and diagnosis of Stuck-At Faults (SAFs) and Transition Faults (TFs). Unfortunately, the algorithms under studied are not able to distinguish between ...
Article history: Received 25 May 2015 Received in revised form 20 June 2015 Accepted 24 June 2015 Available online xxxx
This paper proposes a novel cache architecture for low power consumption, called “Adaptive Way-Predicting Cache (AWP cache).” The AWP cache has multi-operation modes and dynamically adapts the operation mode based on the accuracy of way-prediction results. A confidence counter for way prediction is implemented to each cache set. In order to analyze the effectiveness of the AWP cache, we perform...
Noise margin at read, at write and in stand-by is analyzed for the 6 transistor SRAM cell in a 0.18 μm process considering specific low power conditions such as low supply voltage and source-body biasing. These conditions reduce the noise margin. By using an asymmetrical cell design in which read is performed only on one of the two complementary bit lines, the noise margin can be improved and t...
An ultralow-standby-power technology has been developed in both 0.18m and 0.13m lithography nodes for embedded and standalone SRAM applications. The ultralow-leakage sixtransistor (6T) SRAM cell sizes are 4.81 m and 2.34 m, corresponding respectively to the 0.18m and 0.13m design dimensions. The measured array standby leakage is equal to an average cell leakage current of less than 50 fA per ce...
Building a portfolio of deformations is the key step for building better defect models for the test and yield learning domain. A viable approach to achieve this goal is through geometric characterization and classification of failure patterns found on memory fail bitmaps. In this paper, we present preliminary results on how to build such a portfolio of deformations for an IC technology of inter...
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